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Radio.cpp HEAD (a42f8d32) Text, 65.97 KB
T8b949e// Copyright (c) Sandeep Mistry. All rights reserved.
T8b949e// Licensed under the MIT license.
T8b949e// Modifications and additions copyright 2024 by Mark Qvist & Jacob Eva
T8b949e// Obviously still under the MIT license.
Tff7b72#Tff7b72include T8b949e"Radio.hpp"
Tff7b72#Tff7b72include T8b949e"src/misc/ModemISR.h"
Tff7b72#Tff7b72if PLATFORM == PLATFORM_ESP32
Tff7b72#Tff7b72if defined(ESP32) and !defined(CONFIG_IDF_TARGET_ESP32S3)
Tff7b72#Tff7b72include T8b949e"soc/rtc_wdt.h"
Tff7b72#Tff7b72endif
Tff7b72#Tff7b72define ISR_VECT IRAM_ATTR
Tff7b72#Tff7b72else
Tff7b72#Tff7b72define ISR_VECT
Tff7b72#Tff7b72endif
T8b949e// SX126x registers
Tff7b72#Tff7b72define OP_RF_FREQ_6X 0x86
Tff7b72#Tff7b72define OP_SLEEP_6X 0x84
Tff7b72#Tff7b72define OP_STANDBY_6X 0x80
Tff7b72#Tff7b72define OP_TX_6X 0x83
Tff7b72#Tff7b72define OP_RX_6X 0x82
Tff7b72#Tff7b72define OP_PA_CONFIG_6X 0x95
Tff7b72#Tff7b72define OP_SET_IRQ_FLAGS_6X 0x08 T8b949e// also provides info such as
T8b949e// preamble detection, etc for
T8b949e// knowing when it's safe to switch
T8b949e// antenna modes
Tff7b72#Tff7b72define OP_CLEAR_IRQ_STATUS_6X 0x02
Tff7b72#Tff7b72define OP_GET_IRQ_STATUS_6X 0x12
Tff7b72#Tff7b72define OP_RX_BUFFER_STATUS_6X 0x13
Tff7b72#Tff7b72define OP_PACKET_STATUS_6X 0x14 T8b949e// get snr & rssi of last packet
Tff7b72#Tff7b72define OP_CURRENT_RSSI_6X 0x15
Tff7b72#Tff7b72define OP_MODULATION_PARAMS_6X 0x8B T8b949e// bw, sf, cr, etc.
Tff7b72#Tff7b72define OP_PACKET_PARAMS_6X 0x8C T8b949e// crc, preamble, payload length, etc.
Tff7b72#Tff7b72define OP_STATUS_6X 0xC0
Tff7b72#Tff7b72define OP_TX_PARAMS_6X 0x8E T8b949e// set dbm, etc
Tff7b72#Tff7b72define OP_PACKET_TYPE_6X 0x8A
Tff7b72#Tff7b72define OP_BUFFER_BASE_ADDR_6X 0x8F
Tff7b72#Tff7b72define OP_READ_REGISTER_6X 0x1D
Tff7b72#Tff7b72define OP_WRITE_REGISTER_6X 0x0D
Tff7b72#Tff7b72define OP_DIO3_TCXO_CTRL_6X 0x97
Tff7b72#Tff7b72define OP_DIO2_RF_CTRL_6X 0x9D
Tff7b72#Tff7b72define OP_CAD_PARAMS 0x88
Tff7b72#Tff7b72define OP_CALIBRATE_6X 0x89
Tff7b72#Tff7b72define OP_RX_TX_FALLBACK_MODE_6X 0x93
Tff7b72#Tff7b72define OP_REGULATOR_MODE_6X 0x96
Tff7b72#Tff7b72define OP_CALIBRATE_IMAGE_6X 0x98
Tff7b72#Tff7b72define MASK_CALIBRATE_ALL 0x7f
Tff7b72#Tff7b72define IRQ_TX_DONE_MASK_6X 0x01
Tff7b72#Tff7b72define IRQ_RX_DONE_MASK_6X 0x02
Tff7b72#Tff7b72define IRQ_HEADER_DET_MASK_6X 0x10
Tff7b72#Tff7b72define IRQ_PREAMBLE_DET_MASK_6X 0x04
Tff7b72#Tff7b72define IRQ_PAYLOAD_CRC_ERROR_MASK_6X 0x40
Tff7b72#Tff7b72define IRQ_ALL_MASK_6X 0b0100001111111111
Tff7b72#Tff7b72define MODE_LONG_RANGE_MODE_6X 0x01
Tff7b72#Tff7b72define OP_FIFO_WRITE_6X 0x0E
Tff7b72#Tff7b72define OP_FIFO_READ_6X 0x1E
Tff7b72#Tff7b72define REG_OCP_6X 0x08E7
Tff7b72#Tff7b72define REG_LNA_6X 0x08AC T8b949e// no agc in sx1262
Tff7b72#Tff7b72define REG_SYNC_WORD_MSB_6X 0x0740
Tff7b72#Tff7b72define REG_SYNC_WORD_LSB_6X 0x0741
Tff7b72#Tff7b72define REG_PAYLOAD_LENGTH_6X 0x0702 T8b949e// https://github.com/beegee-tokyo/SX126x-Arduino/blob/master/src/radio/sx126x/sx126x.h#L98
Tff7b72#Tff7b72define REG_RANDOM_GEN_6X 0x0819
Tff7b72#Tff7b72define MODE_TCXO_3_3V_6X 0x07
Tff7b72#Tff7b72define MODE_TCXO_3_0V_6X 0x06
Tff7b72#Tff7b72define MODE_TCXO_2_7V_6X 0x06
Tff7b72#Tff7b72define MODE_TCXO_2_4V_6X 0x06
Tff7b72#Tff7b72define MODE_TCXO_2_2V_6X 0x03
Tff7b72#Tff7b72define MODE_TCXO_1_8V_6X 0x02
Tff7b72#Tff7b72define MODE_TCXO_1_7V_6X 0x01
Tff7b72#Tff7b72define MODE_TCXO_1_6V_6X 0x00
Tff7b72#Tff7b72define MODE_STDBY_RC_6X 0x00
Tff7b72#Tff7b72define MODE_STDBY_XOSC_6X 0x01
Tff7b72#Tff7b72define MODE_FALLBACK_STDBY_RC_6X 0x20
Tff7b72#Tff7b72define MODE_IMPLICIT_HEADER 0x01
Tff7b72#Tff7b72define MODE_EXPLICIT_HEADER 0x00
Tff7b72#Tff7b72define SYNC_WORD_6X 0x1424
Tff7b72#Tff7b72define XTAL_FREQ_6X (double)32000000
Tff7b72#Tff7b72define FREQ_DIV_6X (double)pow(2.0, 25.0)
Tff7b72#Tff7b72define FREQ_STEP_6X (double)(XTAL_FREQ_6X Tff7b72/Tff7b72 FREQ_DIV_6X)
Tff7b72extern Te6edf3FIFOBuffer Te6edf3packet_rdy_interfacesTb4b4b4;
Tff7b72extern Te6edf3RadioInterfaceTff7b72* Te6edf3interface_objTb4b4b4[Tb4b4b4]Tb4b4b4;
Te6edf3sx126xTff7b72:Tff7b72:Te6edf3sx126xTb4b4b4(Tffa657uint8_t Te6edf3indexTb4b4b4, Te6edf3SPIClassTff7b72* Te6edf3spiTb4b4b4, Tffa657bool Te6edf3tcxoTb4b4b4, Tffa657bool Te6edf3dio2_as_rf_switchTb4b4b4, Tffa657int Te6edf3ssTb4b4b4, Tffa657int Te6edf3sclkTb4b4b4, Tffa657int Te6edf3mosiTb4b4b4, Tffa657int Te6edf3misoTb4b4b4, Tffa657int Te6edf3resetTb4b4b4, Tffa657int Te6edf3dio0Tb4b4b4, Tffa657int Te6edf3busyTb4b4b4, Tffa657int Te6edf3rxenTb4b4b4) Tff7b72:
Te6edf3RadioInterfaceTb4b4b4(Te6edf3indexTb4b4b4)Tb4b4b4,
Te6edf3_spiSettingsTb4b4b4(T79c0ff8E6Tb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4, Te6edf3_spiModemTb4b4b4(Te6edf3spiTb4b4b4)Tb4b4b4, Te6edf3_ssTb4b4b4(Te6edf3ssTb4b4b4)Tb4b4b4,
Te6edf3_sclkTb4b4b4(Te6edf3sclkTb4b4b4)Tb4b4b4, Te6edf3_mosiTb4b4b4(Te6edf3mosiTb4b4b4)Tb4b4b4, Te6edf3_misoTb4b4b4(Te6edf3misoTb4b4b4)Tb4b4b4, Te6edf3_resetTb4b4b4(Te6edf3resetTb4b4b4)Tb4b4b4, Te6edf3_dio0Tb4b4b4(Te6edf3dio0Tb4b4b4)Tb4b4b4,
Te6edf3_busyTb4b4b4(Te6edf3busyTb4b4b4)Tb4b4b4, Te6edf3_rxenTb4b4b4(Te6edf3rxenTb4b4b4)Tb4b4b4, Te6edf3_frequencyTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_bwTb4b4b4(T79c0ff0x04Tb4b4b4)Tb4b4b4,
Te6edf3_crTb4b4b4(T79c0ff0x01Tb4b4b4)Tb4b4b4, Te6edf3_packetIndexTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,
Te6edf3_payloadLengthTb4b4b4(T79c0ff255Tb4b4b4)Tb4b4b4, Te6edf3_crcModeTb4b4b4(T79c0ff1Tb4b4b4)Tb4b4b4, Te6edf3_fifo_tx_addr_ptrTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,
Te6edf3_fifo_rx_addr_ptrTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_preinit_doneTb4b4b4(Tffa657falseTb4b4b4)Tb4b4b4, Te6edf3_tcxoTb4b4b4(Te6edf3tcxoTb4b4b4)Tb4b4b4,
Te6edf3_dio2_as_rf_switchTb4b4b4(Te6edf3dio2_as_rf_switchTb4b4b4)
Tb4b4b4{
T8b949e// overide Stream timeout value
Te6edf3setTimeoutTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4;
T8b949e// TODO, figure out why this has to be done. Using the index to reference the
T8b949e// interface_obj list causes a crash otherwise
T8b949e//_index = getIndex();
Tb4b4b4}
Tffa657bool Te6edf3sx126xTff7b72:Tff7b72:Te6edf3preInitTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
T8b949e// todo: check if this change causes issues on any platforms
Tff7b72#Tff7b72if MCU_VARIANT == MCU_ESP32
Tff7b72if Tb4b4b4(Te6edf3_sclk Tff7b72!Tff7b72= T79c0ff-1 Tff7b72&Tff7b72& Te6edf3_miso Tff7b72!Tff7b72= T79c0ff-1 Tff7b72&Tff7b72& Te6edf3_mosi Tff7b72!Tff7b72= T79c0ff-1 Tff7b72&Tff7b72& Te6edf3_ss Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTb4b4b4(Te6edf3_sclkTb4b4b4, Te6edf3_misoTb4b4b4, Te6edf3_mosiTb4b4b4, Te6edf3_ssTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72#Tff7b72else
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
T8b949e// check version (retry for up to 2 seconds)
T8b949e// TODO: Actually read version registers, not syncwords
Tffa657long Te6edf3start Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3syncmsbTb4b4b4;
Tffa657uint8_t Te6edf3synclsbTb4b4b4;
Tff7b72while Tb4b4b4(Tb4b4b4(Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72- Te6edf3startTb4b4b4) Tff7b72< T79c0ff2000Tb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72>Tff7b72= Te6edf3startTb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3syncmsb Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_SYNC_WORD_MSB_6XTb4b4b4)Tb4b4b4;
Te6edf3synclsb Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_SYNC_WORD_LSB_6XTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4( Tffa657uint16_tTb4b4b4(Te6edf3syncmsb Tff7b72<Tff7b72< T79c0ff8 Tff7b72| Te6edf3synclsbTb4b4b4) Tff7b72=Tff7b72= T79c0ff0x1424 Tff7b72|Tff7b72| Tffa657uint16_tTb4b4b4(Te6edf3syncmsb Tff7b72<Tff7b72< T79c0ff8 Tff7b72| Te6edf3synclsbTb4b4b4) Tff7b72=Tff7b72= T79c0ff0x4434Tb4b4b4) Tb4b4b4{
Tff7b72breakTb4b4b4;
Tb4b4b4}
Te6edf3delayTb4b4b4(T79c0ff100Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4( Tffa657uint16_tTb4b4b4(Te6edf3syncmsb Tff7b72<Tff7b72< T79c0ff8 Tff7b72| Te6edf3synclsbTb4b4b4) Tff7b72!Tff7b72= T79c0ff0x1424 Tff7b72&Tff7b72& Tffa657uint16_tTb4b4b4(Te6edf3syncmsb Tff7b72<Tff7b72< T79c0ff8 Tff7b72| Te6edf3synclsbTb4b4b4) Tff7b72!Tff7b72= T79c0ff0x4434Tb4b4b4) Tb4b4b4{
Tff7b72return Tffa657falseTb4b4b4;
Tb4b4b4}
Te6edf3_preinit_done Tff7b72= Tffa657trueTb4b4b4;
Tff7b72return Tffa657trueTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3readRegisterTb4b4b4(Tffa657uint16_t Te6edf3addressTb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3singleTransferTb4b4b4(Te6edf3OP_READ_REGISTER_6XTb4b4b4, Te6edf3addressTb4b4b4, T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3writeRegisterTb4b4b4(Tffa657uint16_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4)
Tb4b4b4{
Te6edf3singleTransferTb4b4b4(Te6edf3OP_WRITE_REGISTER_6XTb4b4b4, Te6edf3addressTb4b4b4, Te6edf3valueTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3singleTransferTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint16_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3responseTb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Tb4b4b4(Te6edf3address Tff7b72& T79c0ff0xFF00Tb4b4b4) Tff7b72>Tff7b72> T79c0ff8Tb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3address Tff7b72& T79c0ff0x00FFTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3opcode Tff7b72=Tff7b72= Te6edf3OP_READ_REGISTER_6XTb4b4b4) Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3response Tff7b72= Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3valueTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3responseTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3digitalWriteTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3loraModeTb4b4b4(Tb4b4b4) Tb4b4b4{
T8b949e// enable lora mode on the SX1262 chip
Tffa657uint8_t Te6edf3mode Tff7b72= Te6edf3MODE_LONG_RANGE_MODE_6XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PACKET_TYPE_6XTb4b4b4, Tff7b72&Te6edf3modeTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3waitOnBusyTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657unsigned Tffa657long Te6edf3time Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_busy Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Tff7b72while Tb4b4b4(Te6edf3digitalReadTb4b4b4(Te6edf3_busyTb4b4b4) Tff7b72=Tff7b72= Te6edf3HIGHTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72>Tff7b72= Tb4b4b4(Te6edf3time Tff7b72+ T79c0ff100Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72breakTb4b4b4; Tb4b4b4}
Tb4b4b4}
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3executeOpcodeTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657uint8_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4)
Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4]Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3executeOpcodeReadTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657uint8_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4)
Tb4b4b4{
Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4] Tff7b72= Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3writeBufferTb4b4b4(Tff7b72const Tffa657uint8_tTff7b72* Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3OP_FIFO_WRITE_6XTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3_fifo_tx_addr_ptrTb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4]Tb4b4b4)Tb4b4b4; Te6edf3_fifo_tx_addr_ptrTff7b72+Tff7b72+Tb4b4b4;Tb4b4b4}
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3readBufferTb4b4b4(Tffa657uint8_tTff7b72* Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3OP_FIFO_READ_6XTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3_fifo_rx_addr_ptrTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4] Tff7b72= Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;Tb4b4b4}
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setModulationParamsTb4b4b4(Tffa657uint8_t Te6edf3sfTb4b4b4, Tffa657uint8_t Te6edf3bwTb4b4b4, Tffa657uint8_t Te6edf3crTb4b4b4, Tffa657int Te6edf3ldroTb4b4b4) Tb4b4b4{
T8b949e// Because there is no access to these registers on the sx1262, we have
T8b949e// to set all these parameters at once or not at all.
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff8Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3sfTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3bwTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Te6edf3crTb4b4b4;
T8b949e// low data rate toggle
Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3ldroTb4b4b4;
T8b949e// unused params in LoRa mode
Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_MODULATION_PARAMS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff8Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setPacketParamsTb4b4b4(Tffa657uint32_t Te6edf3preambleTb4b4b4, Tffa657uint8_t Te6edf3headermodeTb4b4b4, Tffa657uint8_t Te6edf3lengthTb4b4b4, Tffa657uint8_t Te6edf3crcTb4b4b4) Tb4b4b4{
T8b949e// Because there is no access to these registers on the sx1262, we have
T8b949e// to set all these parameters at once or not at all.
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff9Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Tffa657uint8_tTb4b4b4(Tb4b4b4(Te6edf3preamble Tff7b72& T79c0ff0xFF00Tb4b4b4) Tff7b72>Tff7b72> T79c0ff8Tb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Tffa657uint8_tTb4b4b4(Tb4b4b4(Te6edf3preamble Tff7b72& T79c0ff0x00FFTb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Te6edf3headermodeTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3lengthTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Te6edf3crcTb4b4b4;
T8b949e// standard IQ setting (no inversion)
Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
T8b949e// unused params
Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff8Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PACKET_PARAMS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff9Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3resetTb4b4b4(Tffa657voidTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_reset Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
T8b949e// perform reset
Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3calibrateTb4b4b4(Tffa657voidTb4b4b4) Tb4b4b4{
T8b949e// Put in STDBY_RC mode before calibration
Tffa657uint8_t Te6edf3mode_byte Tff7b72= Te6edf3MODE_STDBY_RC_6XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_STANDBY_6XTb4b4b4, Tff7b72&Te6edf3mode_byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
T8b949e// calibrate RC64k, RC13M, PLL, ADC and image
Tffa657uint8_t Te6edf3calibrate Tff7b72= Te6edf3MASK_CALIBRATE_ALLTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CALIBRATE_6XTb4b4b4, Tff7b72&Te6edf3calibrateTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Te6edf3delayTb4b4b4(T79c0ff5Tb4b4b4)Tb4b4b4;
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3calibrate_imageTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3image_freqTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff430E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff440E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x6BTb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x6FTb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff470E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff510E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x75Tb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x81Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff779E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff787E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xC1Tb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xC5Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff863E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff870E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xD7Tb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xDBTb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3frequency Tff7b72>Tff7b72= T79c0ff902E6 Tff7b72&Tff7b72& Te6edf3frequency Tff7b72<Tff7b72= T79c0ff928E6Tb4b4b4) Tb4b4b4{ Te6edf3image_freqTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xE1Tb4b4b4; Te6edf3image_freqTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xE9Tb4b4b4; Tb4b4b4}
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CALIBRATE_IMAGE_6XTb4b4b4, Te6edf3image_freqTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx126xTff7b72:Tff7b72:Te6edf3beginTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3resetTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_busy Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3pinModeTb4b4b4(Te6edf3_busyTb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3_preinit_doneTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3preInitTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{
Tff7b72return Tffa657falseTb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3pinModeTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3calibrateTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3calibrate_imageTb4b4b4(Te6edf3_frequencyTb4b4b4)Tb4b4b4;
Te6edf3enableTCXOTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3loraModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// Set sync word
Te6edf3setSyncWordTb4b4b4(Te6edf3SYNC_WORD_6XTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_dio2_as_rf_switchTb4b4b4) Tb4b4b4{
T8b949e// enable dio2 rf switch
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0x01Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_DIO2_RF_CTRL_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3setFrequencyTb4b4b4(Te6edf3_frequencyTb4b4b4)Tb4b4b4;
Te6edf3setTxPowerTb4b4b4(Te6edf3_txpTb4b4b4)Tb4b4b4;
Te6edf3enableCrcTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// set LNA boost
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_LNA_6XTb4b4b4, T79c0ff0x96Tb4b4b4)Tb4b4b4;
T8b949e// set base addresses
Tffa657uint8_t Te6edf3basebufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_BUFFER_BASE_ADDR_6XTb4b4b4, Te6edf3basebufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4, Te6edf3_ldroTb4b4b4)Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Te6edf3_radio_online Tff7b72= Tffa657trueTb4b4b4;
Tff7b72return T79c0ff1Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3endTb4b4b4(Tb4b4b4)
Tb4b4b4{
T8b949e// put in sleep mode
Te6edf3sleepTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// stop SPI
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3_bitrate Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3_radio_online Tff7b72= Tffa657falseTb4b4b4;
Te6edf3_preinit_done Tff7b72= Tffa657falseTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx126xTff7b72:Tff7b72:Te6edf3beginPacketTb4b4b4(Tffa657int Te6edf3implicitHeaderTb4b4b4)
Tb4b4b4{
Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3implicitHeaderTb4b4b4) Tb4b4b4{
Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3_payloadLength Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3_fifo_tx_addr_ptr Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tff7b72return T79c0ff1Tb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx126xTff7b72:Tff7b72:Te6edf3endPacketTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
T8b949e// put in single TX mode
Tffa657uint8_t Te6edf3timeoutTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_6XTb4b4b4, Te6edf3timeoutTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
T8b949e// Wait for TX done
Tffa657bool Te6edf3timed_out Tff7b72= Tffa657falseTb4b4b4;
Tffa657uint32_t Te6edf3w_timeout Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tff7b72+Tb4b4b4(Te6edf3getAirtimeTb4b4b4(Te6edf3_payloadLengthTb4b4b4)Tff7b72* Te6edf3MODEM_TIMEOUT_MULTTb4b4b4)Tb4b4b4;
Tff7b72while Tb4b4b4(Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72< Te6edf3w_timeoutTb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_TX_DONE_MASK_6XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3yieldTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72> Te6edf3w_timeoutTb4b4b4) Tb4b4b4{ Te6edf3timed_out Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
T8b949e// clear IRQ's
Tffa657uint8_t Te6edf3maskTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3maskTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3maskTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3IRQ_TX_DONE_MASK_6XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_6XTb4b4b4, Te6edf3maskTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tff7b72return Tff7b72!Te6edf3timed_outTb4b4b4;
Tb4b4b4}
Tffa657bool Te6edf3sx126xTff7b72:Tff7b72:Te6edf3dcdTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657bool Te6edf3false_preamble_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tffa657uint32_t Te6edf3now Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tffa657bool Te6edf3header_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3carrier_detected Tff7b72= Tffa657falseTb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_HEADER_DET_MASK_6XTb4b4b4) Tff7b72!Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3header_detected Tff7b72= Tffa657trueTb4b4b4; Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3header_detected Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_PREAMBLE_DET_MASK_6XTb4b4b4) Tff7b72!Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_preamble_detected_at Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3_preamble_detected_at Tff7b72= Te6edf3nowTb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3now Tff7b72- Te6edf3_preamble_detected_at Tff7b72> Te6edf3_lora_preamble_time_ms Tff7b72+ Te6edf3_lora_header_time_msTb4b4b4) Tb4b4b4{
Te6edf3_preamble_detected_at Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3header_detectedTb4b4b4) Tb4b4b4{ Te6edf3false_preamble_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tffa657uint8_t Te6edf3clearbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3clearbufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3IRQ_PREAMBLE_DET_MASK_6XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_6XTb4b4b4, Te6edf3clearbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
T8b949e// TODO: Maybe there's a way of unlatching the RSSI
T8b949e// status without re-activating receive mode?
Tff7b72if Tb4b4b4(Te6edf3false_preamble_detectedTb4b4b4) Tb4b4b4{ Te6edf3receiveTb4b4b4(Tb4b4b4)Tb4b4b4; Te6edf3false_preamble_detected Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}
Tff7b72return Te6edf3carrier_detectedTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3currentRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_CURRENT_RSSI_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3byteTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3currentRssiTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_CURRENT_RSSI_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3rssi Tff7b72= Tff7b72-Tb4b4b4(Tffa657intTb4b4b4(Te6edf3byteTb4b4b4)Tb4b4b4) Tff7b72/ T79c0ff2Tb4b4b4;
Tff7b72return Te6edf3rssiTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3packetRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3packetRssiTb4b4b4(Tffa657uint8_t Te6edf3pkt_snr_rawTb4b4b4) Tb4b4b4{
T8b949e// may need more calculations here
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3pkt_rssi Tff7b72= Tff7b72-Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72/ T79c0ff2Tb4b4b4;
Tff7b72return Te6edf3pkt_rssiTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3packetSnrRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;
Tb4b4b4}
Tffa657float Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3packetSnrTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tff7b72return Tffa657floatTb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4) Tff7b72* T79c0ff0.25Tb4b4b4;
Tb4b4b4}
Tffa657long Te6edf3sx126xTff7b72:Tff7b72:Te6edf3packetFrequencyErrorTb4b4b4(Tb4b4b4)
Tb4b4b4{
T8b949e// todo: implement this, no idea how to check it on the sx1262
Tff7b72const Tffa657float Te6edf3fError Tff7b72= T79c0ff0.0Tb4b4b4;
Tff7b72return Tff7b72static_castTff7b72<Tffa657longTff7b72>Tb4b4b4(Te6edf3fErrorTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657size_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tffa657uint8_t Te6edf3byteTb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3writeTb4b4b4(Tff7b72&Te6edf3byteTb4b4b4, Tff7b72sizeofTb4b4b4(Te6edf3byteTb4b4b4)Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657size_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tff7b72const Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3_payloadLength Tff7b72+ Te6edf3sizeTb4b4b4) Tff7b72> Te6edf3MAX_PKT_LENGTHTb4b4b4) Tb4b4b4{
Te6edf3size Tff7b72= Te6edf3MAX_PKT_LENGTH Tff7b72- Te6edf3_payloadLengthTb4b4b4;
Tb4b4b4}
T8b949e// write data
Te6edf3writeBufferTb4b4b4(Te6edf3bufferTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;
Te6edf3_payloadLength Tff7b72= Te6edf3_payloadLength Tff7b72+ Te6edf3sizeTb4b4b4;
Tff7b72return Te6edf3sizeTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3availableTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72- Te6edf3_packetIndexTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3readTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff-1Tb4b4b4; Tb4b4b4}
T8b949e// if received new packet
Tff7b72if Tb4b4b4(Te6edf3_packetIndex Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_6XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3size Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;
Te6edf3_fifo_rx_addr_ptr Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;
Te6edf3readBufferTb4b4b4(Te6edf3_packetTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3byte Tff7b72= Te6edf3_packetTb4b4b4[Te6edf3_packetIndexTb4b4b4]Tb4b4b4;
Te6edf3_packetIndexTff7b72+Tff7b72+Tb4b4b4;
Tff7b72return Te6edf3byteTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx126xTff7b72:Tff7b72:Te6edf3peekTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{
Tff7b72return T79c0ff-1Tb4b4b4;
Tb4b4b4}
T8b949e// if received new packet
Tff7b72if Tb4b4b4(Te6edf3_packetIndex Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_6XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3size Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;
Te6edf3_fifo_rx_addr_ptr Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;
Te6edf3readBufferTb4b4b4(Te6edf3_packetTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3b Tff7b72= Te6edf3_packetTb4b4b4[Te6edf3_packetIndexTb4b4b4]Tb4b4b4;
Tff7b72return Te6edf3bTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3flushTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3onReceiveTb4b4b4(Tffa657voidTb4b4b4(Tff7b72*Te6edf3callbackTb4b4b4)Tb4b4b4(Tffa657uint8_tTb4b4b4, Tffa657intTb4b4b4)Tb4b4b4)
Tb4b4b4{
Te6edf3_onReceive Tff7b72= Te6edf3callbackTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3callbackTb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_dio0Tb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4;
T8b949e// set preamble and header detection irqs, plus dio0 mask
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff8Tb4b4b4]Tb4b4b4;
T8b949e// set irq masks, enable all
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xFFTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xFFTb4b4b4;
T8b949e// set dio0 masks
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3IRQ_RX_DONE_MASK_6XTb4b4b4;
T8b949e// set dio1 masks
Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
T8b949e// set dio2 masks
Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_SET_IRQ_FLAGS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff8Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3usingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
T8b949e// make function available
Tff7b72extern Tffa657void Tb4b4b4(Tff7b72*Te6edf3onIntRiseTb4b4b4[Te6edf3INTERFACE_COUNTTb4b4b4]Tb4b4b4)Tb4b4b4(Tffa657voidTb4b4b4)Tb4b4b4;
Te6edf3attachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4, Te6edf3onIntRiseTb4b4b4[Te6edf3_indexTb4b4b4]Tb4b4b4, Te6edf3RISINGTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3detachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3notUsingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3receiveTb4b4b4(Tffa657int Te6edf3sizeTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3size Tff7b72> T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// tell radio payload length
Te6edf3_payloadLength Tff7b72= Te6edf3sizeTb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3modeTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0xFFTb4b4b4, T79c0ff0xFFTb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4; T8b949e// continuous mode
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_RX_6XTb4b4b4, Te6edf3modeTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3standbyTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tffa657uint8_t Te6edf3byteTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_tcxoTb4b4b4) Tb4b4b4{
T8b949e// STDBY_XOSC
Te6edf3byte Tff7b72= Te6edf3MODE_STDBY_XOSC_6XTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
T8b949e// STDBY_RC
Te6edf3byte Tff7b72= Te6edf3MODE_STDBY_RC_6XTb4b4b4;
Tb4b4b4}
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_STANDBY_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3sleepTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_SLEEP_6XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3enableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_tcxoTb4b4b4) Tb4b4b4{
Tff7b72#Tff7b72if BOARD_MODEL == BOARD_RAK4631 || BOARD_MODEL == BOARD_OPENCOM_XL || BOARD_MODEL == BOARD_HELTEC32_V3 || BOARD_MODEL == BOARD_XIAO_ESP32S3
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_3_3V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;
Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_TBEAM
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;
Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_TECHO
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;
Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_T3S3
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;
Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_TDECK
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;
Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_TBEAM_S_V1
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;
Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_HELTEC_T114
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;
Tff7b72#Tff7b72elif BOARD_MODEL == BOARD_E22_ESP32
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{Te6edf3MODE_TCXO_1_8V_6XTb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0x00Tb4b4b4, T79c0ff0xFFTb4b4b4}Tb4b4b4;
Tff7b72#Tff7b72else
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Tff7b72#Tff7b72endif
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_DIO3_TCXO_CTRL_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff4Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
T8b949e// TODO: Once enabled, SX1262 needs a complete reset to disable TCXO
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3disableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{ Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setTxPowerTb4b4b4(Tffa657int Te6edf3levelTb4b4b4, Tffa657int Te6edf3outputPinTb4b4b4) Tb4b4b4{
T8b949e// currently no low power mode for SX1262 implemented, assuming PA boost
T8b949e// WORKAROUND - Better Resistance of the SX1262 Tx to Antenna Mismatch, see DS_SX1261-2_V1.2 datasheet chapter 15.2
T8b949e// RegTxClampConfig = @address 0x08D8
Te6edf3writeRegisterTb4b4b4(T79c0ff0x08D8Tb4b4b4, Te6edf3readRegisterTb4b4b4(T79c0ff0x08D8Tb4b4b4) Tff7b72| Tb4b4b4(T79c0ff0x0F Tff7b72<Tff7b72< T79c0ff1Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3pa_bufTb4b4b4[T79c0ff4Tb4b4b4]Tb4b4b4;
Te6edf3pa_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x04Tb4b4b4; T8b949e// PADutyCycle needs to be 0x04 to achieve 22dBm output, but can be lowered for better efficiency at lower outputs
Te6edf3pa_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x07Tb4b4b4; T8b949e// HPMax at 0x07 is maximum supported for SX1262
Te6edf3pa_bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4; T8b949e// DeviceSel 0x00 for SX1262 (0x01 for SX1261)
Te6edf3pa_bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= T79c0ff0x01Tb4b4b4; T8b949e// PALut always 0x01 (reserved according to datasheet)
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PA_CONFIG_6XTb4b4b4, Te6edf3pa_bufTb4b4b4, T79c0ff4Tb4b4b4)Tb4b4b4; T8b949e// set pa_config for high power
Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff22Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff22Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff-9Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff-9Tb4b4b4; Tb4b4b4}
Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_OCP_6XTb4b4b4, Te6edf3OCP_TUNEDTb4b4b4)Tb4b4b4; T8b949e// 160mA limit, overcurrent protection
Tffa657uint8_t Te6edf3tx_bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3levelTb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x02Tb4b4b4; T8b949e// PA ramping time - 40 microseconds
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_PARAMS_6XTb4b4b4, Te6edf3tx_bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657int8_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3getTxPowerTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72return Te6edf3_txpTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setFrequencyTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4) Tb4b4b4{
Te6edf3_frequency Tff7b72= Te6edf3frequencyTb4b4b4;
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4]Tb4b4b4;
Tffa657uint32_t Te6edf3freq Tff7b72= Tb4b4b4(Tffa657uint32_tTb4b4b4)Tb4b4b4(Tb4b4b4(Tffa657doubleTb4b4b4)Te6edf3frequency Tff7b72/ Tb4b4b4(Tffa657doubleTb4b4b4)Te6edf3FREQ_STEP_6XTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff24Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff16Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff8Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4(Te6edf3freq Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_RF_FREQ_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff4Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint32_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3getFrequencyTb4b4b4(Tb4b4b4) Tb4b4b4{
T8b949e// we can't read the frequency on the sx1262 / 80
Tffa657uint32_t Te6edf3frequency Tff7b72= Te6edf3_frequencyTb4b4b4;
Tff7b72return Te6edf3frequencyTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setSpreadingFactorTb4b4b4(Tffa657int Te6edf3sfTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72< T79c0ff5Tb4b4b4) Tb4b4b4{
Te6edf3sf Tff7b72= T79c0ff5Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72> T79c0ff12Tb4b4b4) Tb4b4b4{
Te6edf3sf Tff7b72= T79c0ff12Tb4b4b4;
Tb4b4b4}
Te6edf3_sf Tff7b72= Te6edf3sfTb4b4b4;
Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3setModulationParamsTb4b4b4(Te6edf3sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4, Te6edf3_ldroTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3getSpreadingFactorTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3_sfTb4b4b4;
Tb4b4b4}
Tffa657uint32_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3getSignalBandwidthTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tffa657int Te6edf3bw Tff7b72= Te6edf3_bwTb4b4b4;
Tff7b72switch Tb4b4b4(Te6edf3bwTb4b4b4) Tb4b4b4{
Tff7b72case T79c0ff0x00Tb4b4b4: Tff7b72return T79c0ff7.8E3Tb4b4b4;
Tff7b72case T79c0ff0x01Tb4b4b4: Tff7b72return T79c0ff15.6E3Tb4b4b4;
Tff7b72case T79c0ff0x02Tb4b4b4: Tff7b72return T79c0ff31.25E3Tb4b4b4;
Tff7b72case T79c0ff0x03Tb4b4b4: Tff7b72return T79c0ff62.5E3Tb4b4b4;
Tff7b72case T79c0ff0x04Tb4b4b4: Tff7b72return T79c0ff125E3Tb4b4b4;
Tff7b72case T79c0ff0x05Tb4b4b4: Tff7b72return T79c0ff250E3Tb4b4b4;
Tff7b72case T79c0ff0x06Tb4b4b4: Tff7b72return T79c0ff500E3Tb4b4b4;
Tff7b72case T79c0ff0x08Tb4b4b4: Tff7b72return T79c0ff10.4E3Tb4b4b4;
Tff7b72case T79c0ff0x09Tb4b4b4: Tff7b72return T79c0ff20.8E3Tb4b4b4;
Tff7b72case T79c0ff0x0ATb4b4b4: Tff7b72return T79c0ff41.7E3Tb4b4b4;
Tb4b4b4}
Tff7b72return T79c0ff0Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4{
Tff7b72if Tb4b4b4( Tffa657longTb4b4b4( Tb4b4b4(T79c0ff1Tff7b72<Tff7b72<Te6edf3_sfTb4b4b4) Tff7b72/ Tb4b4b4(Te6edf3getSignalBandwidthTb4b4b4(Tb4b4b4)Tff7b72/T79c0ff1000Tb4b4b4)Tb4b4b4) Tff7b72> T79c0ff16Tb4b4b4) Tb4b4b4{
Te6edf3_ldro Tff7b72= T79c0ff0x01Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3_ldro Tff7b72= T79c0ff0x00Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3optimizeModemSensitivityTb4b4b4(Tb4b4b4)Tb4b4b4{
T8b949e// todo: check if there's anything the sx1262 can do here
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setSignalBandwidthTb4b4b4(Tffa657uint32_t Te6edf3sbwTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff7.8E3Tb4b4b4) Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x00Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff10.4E3Tb4b4b4) Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x08Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff15.6E3Tb4b4b4) Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x01Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff20.8E3Tb4b4b4) Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x09Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff31.25E3Tb4b4b4) Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x02Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff41.7E3Tb4b4b4) Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x0ATb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff62.5E3Tb4b4b4) Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x03Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff125E3Tb4b4b4) Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x04Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff250E3Tb4b4b4) Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x05Tb4b4b4;
Tb4b4b4} Tff7b72else T8b949e/*if (sbw <= 250E3)*/ Tb4b4b4{
Te6edf3_bw Tff7b72= T79c0ff0x06Tb4b4b4;
Tb4b4b4}
Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4, Te6edf3_ldroTb4b4b4)Tb4b4b4;
Te6edf3optimizeModemSensitivityTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setCodingRate4Tb4b4b4(Tffa657int Te6edf3denominatorTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72< T79c0ff5Tb4b4b4) Tb4b4b4{
Te6edf3denominator Tff7b72= T79c0ff5Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72> T79c0ff8Tb4b4b4) Tb4b4b4{
Te6edf3denominator Tff7b72= T79c0ff8Tb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3cr Tff7b72= Te6edf3denominator Tff7b72- T79c0ff4Tb4b4b4;
Te6edf3_cr Tff7b72= Te6edf3crTb4b4b4;
Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3crTb4b4b4, Te6edf3_ldroTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3getCodingRate4Tb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3_cr Tff7b72+ T79c0ff4Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setPreambleLengthTb4b4b4(Tffa657long Te6edf3lengthTb4b4b4)
Tb4b4b4{
Te6edf3_preambleLength Tff7b72= Te6edf3lengthTb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3lengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setSyncWordTb4b4b4(Tffa657uint16_t Te6edf3swTb4b4b4)
Tb4b4b4{
T8b949e// TODO: Why was this hardcoded instead of using the config value?
T8b949e// writeRegister(REG_SYNC_WORD_MSB_6X, (sw & 0xFF00) >> 8);
T8b949e// writeRegister(REG_SYNC_WORD_LSB_6X, sw & 0x00FF);
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_SYNC_WORD_MSB_6XTb4b4b4, T79c0ff0x14Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_SYNC_WORD_LSB_6XTb4b4b4, T79c0ff0x24Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3enableCrcTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3_crcMode Tff7b72= T79c0ff1Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3disableCrcTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3_crcMode Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx126xTff7b72:Tff7b72:Te6edf3randomTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3readRegisterTb4b4b4(Te6edf3REG_RANDOM_GEN_6XTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3setSPIFrequencyTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4)
Tb4b4b4{
Te6edf3_spiSettings Tff7b72= Te6edf3SPISettingsTb4b4b4(Te6edf3frequencyTb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3dumpRegistersTb4b4b4(Te6edf3StreamTff7b72& Te6edf3outTb4b4b4)
Tb4b4b4{
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< T79c0ff128Tb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{
Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Ta5d6ff"Ta5d6ff0xTa5d6ff"Tb4b4b4)Tb4b4b4;
Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Te6edf3iTb4b4b4, Te6edf3HEXTb4b4b4)Tb4b4b4;
Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Ta5d6ff"Ta5d6ff: 0xTa5d6ff"Tb4b4b4)Tb4b4b4;
Te6edf3outTb4b4b4.Te6edf3printlnTb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3iTb4b4b4)Tb4b4b4, Te6edf3HEXTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3_implicitHeaderMode Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3_implicitHeaderMode Tff7b72= T79c0ff1Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx126xTff7b72:Tff7b72:Te6edf3handleDio0RiseTb4b4b4(Tb4b4b4)
Tb4b4b4{
T8b949e// received a packet
Te6edf3_packetIndex Tff7b72= T79c0ff0Tb4b4b4;
T8b949e// read packet length
Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_6XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3packetLength Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_onReceiveTb4b4b4) Tb4b4b4{
Te6edf3_onReceiveTb4b4b4(Te6edf3_indexTb4b4b4, Te6edf3packetLengthTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657bool Te6edf3ISR_VECT Te6edf3sx126xTff7b72:Tff7b72:Te6edf3getPacketValidityTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_6XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_PAYLOAD_CRC_ERROR_MASK_6XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Tff7b72return Tffa657trueTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Tff7b72return Tffa657falseTb4b4b4;
Tb4b4b4}
Tb4b4b4}
T8b949e// SX127x registers
Tff7b72#Tff7b72define REG_FIFO_7X 0x00
Tff7b72#Tff7b72define REG_OP_MODE_7X 0x01
Tff7b72#Tff7b72define REG_FRF_MSB_7X 0x06
Tff7b72#Tff7b72define REG_FRF_MID_7X 0x07
Tff7b72#Tff7b72define REG_FRF_LSB_7X 0x08
Tff7b72#Tff7b72define REG_PA_CONFIG_7X 0x09
Tff7b72#Tff7b72define REG_OCP_7X 0x0b
Tff7b72#Tff7b72define REG_LNA_7X 0x0c
Tff7b72#Tff7b72define REG_FIFO_ADDR_PTR_7X 0x0d
Tff7b72#Tff7b72define REG_FIFO_TX_BASE_ADDR_7X 0x0e
Tff7b72#Tff7b72define REG_FIFO_RX_BASE_ADDR_7X 0x0f
Tff7b72#Tff7b72define REG_FIFO_RX_CURRENT_ADDR_7X 0x10
Tff7b72#Tff7b72define REG_IRQ_FLAGS_7X 0x12
Tff7b72#Tff7b72define REG_RX_NB_BYTES_7X 0x13
Tff7b72#Tff7b72define REG_MODEM_STAT_7X 0x18
Tff7b72#Tff7b72define REG_PKT_SNR_VALUE_7X 0x19
Tff7b72#Tff7b72define REG_PKT_RSSI_VALUE_7X 0x1a
Tff7b72#Tff7b72define REG_RSSI_VALUE_7X 0x1b
Tff7b72#Tff7b72define REG_MODEM_CONFIG_1_7X 0x1d
Tff7b72#Tff7b72define REG_MODEM_CONFIG_2_7X 0x1e
Tff7b72#Tff7b72define REG_PREAMBLE_MSB_7X 0x20
Tff7b72#Tff7b72define REG_PREAMBLE_LSB_7X 0x21
Tff7b72#Tff7b72define REG_PAYLOAD_LENGTH_7X 0x22
Tff7b72#Tff7b72define REG_MODEM_CONFIG_3_7X 0x26
Tff7b72#Tff7b72define REG_FREQ_ERROR_MSB_7X 0x28
Tff7b72#Tff7b72define REG_FREQ_ERROR_MID_7X 0x29
Tff7b72#Tff7b72define REG_FREQ_ERROR_LSB_7X 0x2a
Tff7b72#Tff7b72define REG_RSSI_WIDEBAND_7X 0x2c
Tff7b72#Tff7b72define REG_DETECTION_OPTIMIZE_7X 0x31
Tff7b72#Tff7b72define REG_HIGH_BW_OPTIMIZE_1_7X 0x36
Tff7b72#Tff7b72define REG_DETECTION_THRESHOLD_7X 0x37
Tff7b72#Tff7b72define REG_SYNC_WORD_7X 0x39
Tff7b72#Tff7b72define REG_HIGH_BW_OPTIMIZE_2_7X 0x3a
Tff7b72#Tff7b72define REG_DIO_MAPPING_1_7X 0x40
Tff7b72#Tff7b72define REG_VERSION_7X 0x42
Tff7b72#Tff7b72define REG_TCXO_7X 0x4b
Tff7b72#Tff7b72define REG_PA_DAC_7X 0x4d
T8b949e// Modes
Tff7b72#Tff7b72define MODE_LONG_RANGE_MODE_7X 0x80
Tff7b72#Tff7b72define MODE_SLEEP_7X 0x00
Tff7b72#Tff7b72define MODE_STDBY_7X 0x01
Tff7b72#Tff7b72define MODE_TX_7X 0x03
Tff7b72#Tff7b72define MODE_RX_CONTINUOUS_7X 0x05
Tff7b72#Tff7b72define MODE_RX_SINGLE_7X 0x06
T8b949e// PA config
Tff7b72#Tff7b72define PA_BOOST_7X 0x80
T8b949e// IRQ masks
Tff7b72#Tff7b72define IRQ_TX_DONE_MASK_7X 0x08
Tff7b72#Tff7b72define IRQ_RX_DONE_MASK_7X 0x40
Tff7b72#Tff7b72define IRQ_PAYLOAD_CRC_ERROR_MASK_7X 0x20
Tff7b72#Tff7b72define SYNC_WORD_7X 0x12
Te6edf3sx127xTff7b72:Tff7b72:Te6edf3sx127xTb4b4b4(Tffa657uint8_t Te6edf3indexTb4b4b4, Te6edf3SPIClassTff7b72* Te6edf3spiTb4b4b4, Tffa657int Te6edf3ssTb4b4b4, Tffa657int Te6edf3sclkTb4b4b4, Tffa657int Te6edf3mosiTb4b4b4, Tffa657int Te6edf3misoTb4b4b4, Tffa657int Te6edf3resetTb4b4b4, Tffa657int Te6edf3dio0Tb4b4b4, Tffa657int Te6edf3busyTb4b4b4) Tff7b72:
Te6edf3RadioInterfaceTb4b4b4(Te6edf3indexTb4b4b4)Tb4b4b4,
Te6edf3_spiSettingsTb4b4b4(T79c0ff8E6Tb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4,
Te6edf3_spiModemTb4b4b4(Te6edf3spiTb4b4b4)Tb4b4b4,
Te6edf3_ssTb4b4b4(Te6edf3ssTb4b4b4)Tb4b4b4, Te6edf3_sclkTb4b4b4(Te6edf3sclkTb4b4b4)Tb4b4b4, Te6edf3_mosiTb4b4b4(Te6edf3mosiTb4b4b4)Tb4b4b4, Te6edf3_misoTb4b4b4(Te6edf3misoTb4b4b4)Tb4b4b4, Te6edf3_resetTb4b4b4(Te6edf3resetTb4b4b4)Tb4b4b4, Te6edf3_dio0Tb4b4b4(Te6edf3dio0Tb4b4b4)Tb4b4b4,
Te6edf3_busyTb4b4b4(Te6edf3busyTb4b4b4)Tb4b4b4, Te6edf3_frequencyTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_packetIndexTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_preinit_doneTb4b4b4(Tffa657falseTb4b4b4)Tb4b4b4, Te6edf3_bwTb4b4b4(T79c0ff7800Tb4b4b4)
Tb4b4b4{ Te6edf3setTimeoutTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3setSPIFrequencyTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4) Tb4b4b4{ Te6edf3_spiSettings Tff7b72= Te6edf3SPISettingsTb4b4b4(Te6edf3frequencyTb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3readRegisterTb4b4b4(Tffa657uint8_t Te6edf3addressTb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3singleTransferTb4b4b4(Te6edf3address Tff7b72& T79c0ff0x7fTb4b4b4, T79c0ff0x00Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3writeRegisterTb4b4b4(Tffa657uint8_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4) Tb4b4b4{ Te6edf3singleTransferTb4b4b4(Te6edf3address Tff7b72| T79c0ff0x80Tb4b4b4, Te6edf3valueTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3standbyTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(Te6edf3REG_OP_MODE_7XTb4b4b4, Te6edf3MODE_LONG_RANGE_MODE_7X Tff7b72| Te6edf3MODE_STDBY_7XTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3sleepTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(Te6edf3REG_OP_MODE_7XTb4b4b4, Te6edf3MODE_LONG_RANGE_MODE_7X Tff7b72| Te6edf3MODE_SLEEP_7XTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3setSyncWordTb4b4b4(Tffa657uint8_t Te6edf3swTb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(Te6edf3REG_SYNC_WORD_7XTb4b4b4, Te6edf3swTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3enableCrcTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_2_7XTb4b4b4, Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_2_7XTb4b4b4) Tff7b72| T79c0ff0x04Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3disableCrcTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_2_7XTb4b4b4, Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_2_7XTb4b4b4) Tff7b72& T79c0ff0xfbTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3enableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{ Tffa657uint8_t Te6edf3tcxo_reg Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_TCXO_7XTb4b4b4)Tb4b4b4; Te6edf3writeRegisterTb4b4b4(Te6edf3REG_TCXO_7XTb4b4b4, Te6edf3tcxo_reg Tff7b72| T79c0ff0x10Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3disableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{ Tffa657uint8_t Te6edf3tcxo_reg Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_TCXO_7XTb4b4b4)Tb4b4b4; Te6edf3writeRegisterTb4b4b4(Te6edf3REG_TCXO_7XTb4b4b4, Te6edf3tcxo_reg Tff7b72& T79c0ff0xEFTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_implicitHeaderMode Tff7b72= T79c0ff0Tb4b4b4; Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_1_7XTb4b4b4, Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_1_7XTb4b4b4) Tff7b72& T79c0ff0xfeTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4) Tb4b4b4{ Te6edf3_implicitHeaderMode Tff7b72= T79c0ff1Tb4b4b4; Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_1_7XTb4b4b4, Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_1_7XTb4b4b4) Tff7b72| T79c0ff0x01Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657uint8_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3randomTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3readRegisterTb4b4b4(Te6edf3REG_RSSI_WIDEBAND_7XTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3flushTb4b4b4(Tb4b4b4) Tb4b4b4{ Tb4b4b4}
Tffa657bool Te6edf3sx127xTff7b72:Tff7b72:Te6edf3preInitTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
T8b949e// todo: check if this change causes issues on any platforms
Tff7b72#Tff7b72if MCU_VARIANT == MCU_ESP32
Tff7b72if Tb4b4b4(Te6edf3_sclk Tff7b72!Tff7b72= T79c0ff-1 Tff7b72&Tff7b72& Te6edf3_miso Tff7b72!Tff7b72= T79c0ff-1 Tff7b72&Tff7b72& Te6edf3_mosi Tff7b72!Tff7b72= T79c0ff-1 Tff7b72&Tff7b72& Te6edf3_ss Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTb4b4b4(Te6edf3_sclkTb4b4b4, Te6edf3_misoTb4b4b4, Te6edf3_mosiTb4b4b4, Te6edf3_ssTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72#Tff7b72else
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
T8b949e// Check modem version
Tffa657uint8_t Te6edf3versionTb4b4b4;
Tffa657long Te6edf3start Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72while Tb4b4b4(Tb4b4b4(Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72- Te6edf3startTb4b4b4) Tff7b72< T79c0ff500Tb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72>Tff7b72= Te6edf3startTb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3version Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_VERSION_7XTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3version Tff7b72=Tff7b72= T79c0ff0x12Tb4b4b4) Tb4b4b4{ Tff7b72breakTb4b4b4; Tb4b4b4}
Te6edf3delayTb4b4b4(T79c0ff100Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3version Tff7b72!Tff7b72= T79c0ff0x12Tb4b4b4) Tb4b4b4{ Tff7b72return Tffa657falseTb4b4b4; Tb4b4b4}
Te6edf3_preinit_done Tff7b72= Tffa657trueTb4b4b4;
Tff7b72return Tffa657trueTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3singleTransferTb4b4b4(Tffa657uint8_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3responseTb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3addressTb4b4b4)Tb4b4b4;
Te6edf3response Tff7b72= Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3valueTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3responseTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3resetTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_reset Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
T8b949e// Perform reset
Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657int Te6edf3sx127xTff7b72:Tff7b72:Te6edf3beginTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3resetTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3sleepTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_busy Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3pinModeTb4b4b4(Te6edf3_busyTb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3_preinit_doneTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3preInitTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return Tffa657falseTb4b4b4; Tb4b4b4}
Tb4b4b4}
Te6edf3setFrequencyTb4b4b4(Te6edf3_frequencyTb4b4b4)Tb4b4b4;
Te6edf3setSignalBandwidthTb4b4b4(Te6edf3_bwTb4b4b4)Tb4b4b4;
Te6edf3setSpreadingFactorTb4b4b4(Te6edf3_sfTb4b4b4)Tb4b4b4;
Te6edf3setCodingRate4Tb4b4b4(Te6edf3_crTb4b4b4)Tb4b4b4;
Te6edf3setTxPowerTb4b4b4(Te6edf3_txpTb4b4b4)Tb4b4b4;
T8b949e// Set base addresses
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FIFO_TX_BASE_ADDR_7XTb4b4b4, T79c0ff0Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FIFO_RX_BASE_ADDR_7XTb4b4b4, T79c0ff0Tb4b4b4)Tb4b4b4;
T8b949e// Set LNA boost and auto AGC
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_LNA_7XTb4b4b4, Te6edf3readRegisterTb4b4b4(Te6edf3REG_LNA_7XTb4b4b4) Tff7b72| T79c0ff0x03Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_3_7XTb4b4b4, T79c0ff0x04Tb4b4b4)Tb4b4b4;
Te6edf3setSyncWordTb4b4b4(Te6edf3SYNC_WORD_7XTb4b4b4)Tb4b4b4;
Te6edf3enableCrcTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3_radio_online Tff7b72= Tffa657trueTb4b4b4;
Tff7b72return T79c0ff1Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3endTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3sleepTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3_bitrate Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3_radio_online Tff7b72= Tffa657falseTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx127xTff7b72:Tff7b72:Te6edf3beginPacketTb4b4b4(Tffa657int Te6edf3implicitHeaderTb4b4b4) Tb4b4b4{
Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3implicitHeaderTb4b4b4) Tb4b4b4{
Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
T8b949e// Reset FIFO address and payload length
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FIFO_ADDR_PTR_7XTb4b4b4, T79c0ff0Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_PAYLOAD_LENGTH_7XTb4b4b4, T79c0ff0Tb4b4b4)Tb4b4b4;
Tff7b72return T79c0ff1Tb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx127xTff7b72:Tff7b72:Te6edf3endPacketTb4b4b4(Tb4b4b4) Tb4b4b4{
T8b949e// Enter TX mode
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_OP_MODE_7XTb4b4b4, Te6edf3MODE_LONG_RANGE_MODE_7X Tff7b72| Te6edf3MODE_TX_7XTb4b4b4)Tb4b4b4;
T8b949e// Wait for TX completion
Tff7b72while Tb4b4b4(Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_IRQ_FLAGS_7XTb4b4b4) Tff7b72& Te6edf3IRQ_TX_DONE_MASK_7XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3yieldTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
T8b949e// Clear TX complete IRQ
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_IRQ_FLAGS_7XTb4b4b4, Te6edf3IRQ_TX_DONE_MASK_7XTb4b4b4)Tb4b4b4;
Tff7b72return T79c0ff1Tb4b4b4;
Tb4b4b4}
Tffa657bool Te6edf3sx127xTff7b72:Tff7b72:Te6edf3dcdTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657bool Te6edf3carrier_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657uint8_t Te6edf3status Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_STAT_7XTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3status Tff7b72& Te6edf3SIG_DETECTTb4b4b4) Tff7b72=Tff7b72= Te6edf3SIG_DETECTTb4b4b4) Tb4b4b4{ Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3status Tff7b72& Te6edf3SIG_SYNCEDTb4b4b4) Tff7b72=Tff7b72= Te6edf3SIG_SYNCEDTb4b4b4) Tb4b4b4{ Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tff7b72return Te6edf3carrier_detectedTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3currentRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3rssi Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_RSSI_VALUE_7XTb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3rssiTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3currentRssiTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657int Te6edf3rssi Tff7b72= Tb4b4b4(Tffa657intTb4b4b4)Te6edf3readRegisterTb4b4b4(Te6edf3REG_RSSI_VALUE_7XTb4b4b4) Tff7b72- Te6edf3RSSI_OFFSETTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_frequency Tff7b72< T79c0ff820E6Tb4b4b4) Te6edf3rssi Tff7b72-Tff7b72= T79c0ff7Tb4b4b4;
Tff7b72return Te6edf3rssiTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3packetRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3pkt_rssi_value Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_PKT_RSSI_VALUE_7XTb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3pkt_rssi_valueTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3packetRssiTb4b4b4(Tffa657uint8_t Te6edf3pkt_snr_rawTb4b4b4) Tb4b4b4{
Tffa657int Te6edf3pkt_rssi Tff7b72= Tb4b4b4(Tffa657intTb4b4b4)Te6edf3readRegisterTb4b4b4(Te6edf3REG_PKT_RSSI_VALUE_7XTb4b4b4) Tff7b72- Te6edf3RSSI_OFFSETTb4b4b4;
Tffa657int Te6edf3pkt_snr Tff7b72= Tb4b4b4(Tb4b4b4(Tffa657int8_tTb4b4b4)Te6edf3pkt_snr_rawTb4b4b4)Tff7b72*T79c0ff0.25Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_frequency Tff7b72< T79c0ff820E6Tb4b4b4) Te6edf3pkt_rssi Tff7b72-Tff7b72= T79c0ff7Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3pkt_snr Tff7b72< T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3pkt_rssi Tff7b72+Tff7b72= Te6edf3pkt_snrTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
T8b949e// Slope correction is (16/15)*pkt_rssi,
T8b949e// this estimation looses one floating point
T8b949e// operation, and should be precise enough.
Te6edf3pkt_rssi Tff7b72= Tb4b4b4(Tffa657intTb4b4b4)Tb4b4b4(T79c0ff1.066 Tff7b72* Te6edf3pkt_rssiTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72return Te6edf3pkt_rssiTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3packetRssiTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657int Te6edf3pkt_rssi Tff7b72= Tb4b4b4(Tffa657intTb4b4b4)Te6edf3readRegisterTb4b4b4(Te6edf3REG_PKT_RSSI_VALUE_7XTb4b4b4) Tff7b72- Te6edf3RSSI_OFFSETTb4b4b4;
Tffa657int Te6edf3pkt_snr Tff7b72= Te6edf3packetSnrTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_frequency Tff7b72< T79c0ff820E6Tb4b4b4) Te6edf3pkt_rssi Tff7b72-Tff7b72= T79c0ff7Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3pkt_snr Tff7b72< T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3pkt_rssi Tff7b72+Tff7b72= Te6edf3pkt_snrTb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{
T8b949e// Slope correction is (16/15)*pkt_rssi,
T8b949e// this estimation looses one floating point
T8b949e// operation, and should be precise enough.
Te6edf3pkt_rssi Tff7b72= Tb4b4b4(Tffa657intTb4b4b4)Tb4b4b4(T79c0ff1.066 Tff7b72* Te6edf3pkt_rssiTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72return Te6edf3pkt_rssiTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3packetSnrRawTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3readRegisterTb4b4b4(Te6edf3REG_PKT_SNR_VALUE_7XTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657float Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3packetSnrTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Tb4b4b4(Tb4b4b4(Tffa657int8_tTb4b4b4)Te6edf3readRegisterTb4b4b4(Te6edf3REG_PKT_SNR_VALUE_7XTb4b4b4)Tb4b4b4) Tff7b72* T79c0ff0.25Tb4b4b4; Tb4b4b4}
Tffa657long Te6edf3sx127xTff7b72:Tff7b72:Te6edf3packetFrequencyErrorTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657int32_t Te6edf3freqError Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3freqError Tff7b72= Tff7b72static_castTff7b72<Tffa657int32_tTff7b72>Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_FREQ_ERROR_MSB_7XTb4b4b4) Tff7b72& Te6edf3B111Tb4b4b4)Tb4b4b4;
Te6edf3freqError Tff7b72<Tff7b72<Tff7b72= T79c0ff8LTb4b4b4;
Te6edf3freqError Tff7b72+Tff7b72= Tff7b72static_castTff7b72<Tffa657int32_tTff7b72>Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_FREQ_ERROR_MID_7XTb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3freqError Tff7b72<Tff7b72<Tff7b72= T79c0ff8LTb4b4b4;
Te6edf3freqError Tff7b72+Tff7b72= Tff7b72static_castTff7b72<Tffa657int32_tTff7b72>Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_FREQ_ERROR_LSB_7XTb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_FREQ_ERROR_MSB_7XTb4b4b4) Tff7b72& Te6edf3B1000Tb4b4b4) Tb4b4b4{ T8b949e// Sign bit is on
Te6edf3freqError Tff7b72-Tff7b72= T79c0ff524288Tb4b4b4; T8b949e// B1000'0000'0000'0000'0000
Tb4b4b4}
Tff7b72const Tffa657float Te6edf3fXtal Tff7b72= T79c0ff32E6Tb4b4b4; T8b949e// FXOSC: crystal oscillator (XTAL) frequency (2.5. Chip Specification, p. 14)
Tff7b72const Tffa657float Te6edf3fError Tff7b72= Tb4b4b4(Tb4b4b4(Tff7b72static_castTff7b72<Tffa657floatTff7b72>Tb4b4b4(Te6edf3freqErrorTb4b4b4) Tff7b72* Tb4b4b4(T79c0ff1L Tff7b72<Tff7b72< T79c0ff24Tb4b4b4)Tb4b4b4) Tff7b72/ Te6edf3fXtalTb4b4b4) Tff7b72* Tb4b4b4(Te6edf3getSignalBandwidthTb4b4b4(Tb4b4b4) Tff7b72/ T79c0ff500000.0fTb4b4b4)Tb4b4b4;
Tff7b72return Tff7b72static_castTff7b72<Tffa657longTff7b72>Tb4b4b4(Te6edf3fErrorTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657size_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tffa657uint8_t Te6edf3byteTb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3writeTb4b4b4(Tff7b72&Te6edf3byteTb4b4b4, Tff7b72sizeofTb4b4b4(Te6edf3byteTb4b4b4)Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657size_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tff7b72const Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4) Tb4b4b4{
Tffa657int Te6edf3currentLength Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_PAYLOAD_LENGTH_7XTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3currentLength Tff7b72+ Te6edf3sizeTb4b4b4) Tff7b72> Te6edf3MAX_PKT_LENGTHTb4b4b4) Tb4b4b4{ Te6edf3size Tff7b72= Te6edf3MAX_PKT_LENGTH Tff7b72- Te6edf3currentLengthTb4b4b4; Tb4b4b4}
Tff7b72for Tb4b4b4(Tffa657size_t Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FIFO_7XTb4b4b4, Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4]Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_PAYLOAD_LENGTH_7XTb4b4b4, Te6edf3currentLength Tff7b72+ Te6edf3sizeTb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3sizeTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3availableTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_RX_NB_BYTES_7XTb4b4b4) Tff7b72- Te6edf3_packetIndexTb4b4b4)Tb4b4b4; Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3readTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff-1Tb4b4b4; Tb4b4b4}
Te6edf3_packetIndexTff7b72+Tff7b72+Tb4b4b4;
Tff7b72return Te6edf3readRegisterTb4b4b4(Te6edf3REG_FIFO_7XTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx127xTff7b72:Tff7b72:Te6edf3peekTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff-1Tb4b4b4; Tb4b4b4}
T8b949e// Remember current FIFO address, read, and then reset address
Tffa657int Te6edf3currentAddress Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_FIFO_ADDR_PTR_7XTb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3b Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_FIFO_7XTb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FIFO_ADDR_PTR_7XTb4b4b4, Te6edf3currentAddressTb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3bTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3onReceiveTb4b4b4(Tffa657voidTb4b4b4(Tff7b72*Te6edf3callbackTb4b4b4)Tb4b4b4(Tffa657uint8_tTb4b4b4, Tffa657intTb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3_onReceive Tff7b72= Te6edf3callbackTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3callbackTb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_dio0Tb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_DIO_MAPPING_1_7XTb4b4b4, T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3usingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
T8b949e// make function available
Tff7b72extern Tffa657void Tb4b4b4(Tff7b72*Te6edf3onIntRiseTb4b4b4[Te6edf3INTERFACE_COUNTTb4b4b4]Tb4b4b4)Tb4b4b4(Tffa657voidTb4b4b4)Tb4b4b4;
Te6edf3attachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4, Te6edf3onIntRiseTb4b4b4[Te6edf3_indexTb4b4b4]Tb4b4b4, Te6edf3RISINGTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3detachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3notUsingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3receiveTb4b4b4(Tffa657int Te6edf3sizeTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3size Tff7b72> T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_PAYLOAD_LENGTH_7XTb4b4b4, Te6edf3size Tff7b72& T79c0ff0xffTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{ Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_OP_MODE_7XTb4b4b4, Te6edf3MODE_LONG_RANGE_MODE_7X Tff7b72| Te6edf3MODE_RX_CONTINUOUS_7XTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3setTxPowerTb4b4b4(Tffa657int Te6edf3levelTb4b4b4, Tffa657int Te6edf3outputPinTb4b4b4) Tb4b4b4{
T8b949e// Setup according to RFO or PA_BOOST output pin
Tff7b72if Tb4b4b4(Te6edf3PA_OUTPUT_RFO_PIN Tff7b72=Tff7b72= Te6edf3outputPinTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff0Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff14Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff14Tb4b4b4; Tb4b4b4}
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_PA_DAC_7XTb4b4b4, T79c0ff0x84Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_PA_CONFIG_7XTb4b4b4, T79c0ff0x70 Tff7b72| Te6edf3levelTb4b4b4)Tb4b4b4;
Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff2Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff2Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff17Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff17Tb4b4b4; Tb4b4b4}
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_PA_DAC_7XTb4b4b4, T79c0ff0x84Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_PA_CONFIG_7XTb4b4b4, Te6edf3PA_BOOST_7X Tff7b72| Tb4b4b4(Te6edf3level Tff7b72- T79c0ff2Tb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657int8_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3getTxPowerTb4b4b4(Tb4b4b4) Tb4b4b4{ Tff7b72return Te6edf3readRegisterTb4b4b4(Te6edf3REG_PA_CONFIG_7XTb4b4b4) Tff7b72- T79c0ff126Tb4b4b4; Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3setFrequencyTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4) Tb4b4b4{
Te6edf3_frequency Tff7b72= Te6edf3frequencyTb4b4b4;
Tffa657uint32_t Te6edf3frf Tff7b72= Tb4b4b4(Tb4b4b4(Tffa657uint64_tTb4b4b4)Te6edf3frequency Tff7b72<Tff7b72< T79c0ff19Tb4b4b4) Tff7b72/ T79c0ff32000000Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FRF_MSB_7XTb4b4b4, Tb4b4b4(Tffa657uint8_tTb4b4b4)Tb4b4b4(Te6edf3frf Tff7b72>Tff7b72> T79c0ff16Tb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FRF_MID_7XTb4b4b4, Tb4b4b4(Tffa657uint8_tTb4b4b4)Tb4b4b4(Te6edf3frf Tff7b72>Tff7b72> T79c0ff8Tb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FRF_LSB_7XTb4b4b4, Tb4b4b4(Tffa657uint8_tTb4b4b4)Tb4b4b4(Te6edf3frf Tff7b72>Tff7b72> T79c0ff0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3optimizeModemSensitivityTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint32_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3getFrequencyTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72return Te6edf3_frequencyTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3setSpreadingFactorTb4b4b4(Tffa657int Te6edf3sfTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72< T79c0ff6Tb4b4b4) Tb4b4b4{ Te6edf3sf Tff7b72= T79c0ff6Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72> T79c0ff12Tb4b4b4) Tb4b4b4{ Te6edf3sf Tff7b72= T79c0ff12Tb4b4b4; Tb4b4b4}
Te6edf3_sf Tff7b72= Te6edf3sfTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72=Tff7b72= T79c0ff6Tb4b4b4) Tb4b4b4{
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_DETECTION_OPTIMIZE_7XTb4b4b4, T79c0ff0xc5Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_DETECTION_THRESHOLD_7XTb4b4b4, T79c0ff0x0cTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_DETECTION_OPTIMIZE_7XTb4b4b4, T79c0ff0xc3Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_DETECTION_THRESHOLD_7XTb4b4b4, T79c0ff0x0aTb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_2_7XTb4b4b4, Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_2_7XTb4b4b4) Tff7b72& T79c0ff0x0fTb4b4b4) Tff7b72| Tb4b4b4(Tb4b4b4(Te6edf3sf Tff7b72<Tff7b72< T79c0ff4Tb4b4b4) Tff7b72& T79c0ff0xf0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3getSpreadingFactorTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3_sfTb4b4b4;
Tb4b4b4}
Tffa657uint32_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3getSignalBandwidthTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72return Te6edf3_bwTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3setSignalBandwidthTb4b4b4(Tffa657uint32_t Te6edf3sbwTb4b4b4) Tb4b4b4{
Tffa657int Te6edf3bwTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff7.8E3Tb4b4b4) Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff0Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff10.4E3Tb4b4b4) Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff1Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff15.6E3Tb4b4b4) Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff2Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff20.8E3Tb4b4b4) Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff3Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff31.25E3Tb4b4b4) Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff4Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff41.7E3Tb4b4b4) Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff5Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff62.5E3Tb4b4b4) Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff6Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff125E3Tb4b4b4) Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff7Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff250E3Tb4b4b4) Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff8Tb4b4b4;
Tb4b4b4} Tff7b72else T8b949e/*if (sbw <= 250E3)*/ Tb4b4b4{
Te6edf3bw Tff7b72= T79c0ff9Tb4b4b4;
Tb4b4b4}
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_1_7XTb4b4b4, Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_1_7XTb4b4b4) Tff7b72& T79c0ff0x0fTb4b4b4) Tff7b72| Tb4b4b4(Te6edf3bw Tff7b72<Tff7b72< T79c0ff4Tb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3_bw Tff7b72= Te6edf3sbwTb4b4b4;
Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3optimizeModemSensitivityTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3setCodingRate4Tb4b4b4(Tffa657int Te6edf3denominatorTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72< T79c0ff5Tb4b4b4) Tb4b4b4{ Te6edf3denominator Tff7b72= T79c0ff5Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72> T79c0ff8Tb4b4b4) Tb4b4b4{ Te6edf3denominator Tff7b72= T79c0ff8Tb4b4b4; Tb4b4b4}
Tffa657int Te6edf3cr Tff7b72= Te6edf3denominator Tff7b72- T79c0ff4Tb4b4b4;
Te6edf3_cr Tff7b72= Te6edf3crTb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_1_7XTb4b4b4, Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_1_7XTb4b4b4) Tff7b72& T79c0ff0xf1Tb4b4b4) Tff7b72| Tb4b4b4(Te6edf3cr Tff7b72<Tff7b72< T79c0ff1Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx127xTff7b72:Tff7b72:Te6edf3getCodingRate4Tb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3_cr Tff7b72+ T79c0ff4Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3setPreambleLengthTb4b4b4(Tffa657long Te6edf3lengthTb4b4b4) Tb4b4b4{
Te6edf3_preambleLength Tff7b72= Te6edf3lengthTb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_PREAMBLE_MSB_7XTb4b4b4, Tb4b4b4(Tffa657uint8_tTb4b4b4)Tb4b4b4(Te6edf3length Tff7b72>Tff7b72> T79c0ff8Tb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_PREAMBLE_LSB_7XTb4b4b4, Tb4b4b4(Tffa657uint8_tTb4b4b4)Tb4b4b4(Te6edf3length Tff7b72>Tff7b72> T79c0ff0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657int Te6edf3sf Tff7b72= Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_2_7XTb4b4b4) Tff7b72>Tff7b72> T79c0ff4Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4( Tffa657longTb4b4b4( Tb4b4b4(T79c0ff1Tff7b72<Tff7b72<Te6edf3sfTb4b4b4) Tff7b72/ Tb4b4b4(Te6edf3getSignalBandwidthTb4b4b4(Tb4b4b4)Tff7b72/T79c0ff1000Tb4b4b4)Tb4b4b4) Tff7b72> T79c0ff16Tb4b4b4) Tb4b4b4{
T8b949e// Set auto AGC and LowDataRateOptimize
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_3_7XTb4b4b4, Tb4b4b4(T79c0ff1Tff7b72<Tff7b72<T79c0ff3Tb4b4b4)Tff7b72|Tb4b4b4(T79c0ff1Tff7b72<Tff7b72<T79c0ff2Tb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3_ldro Tff7b72= Tffa657trueTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
T8b949e// Only set auto AGC
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_3_7XTb4b4b4, Tb4b4b4(T79c0ff1Tff7b72<Tff7b72<T79c0ff2Tb4b4b4)Tb4b4b4)Tb4b4b4;
Te6edf3_ldro Tff7b72= Tffa657falseTb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3optimizeModemSensitivityTb4b4b4(Tb4b4b4) Tb4b4b4{
Te6edf3byte Te6edf3bw Tff7b72= Tb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3REG_MODEM_CONFIG_1_7XTb4b4b4) Tff7b72>Tff7b72> T79c0ff4Tb4b4b4)Tb4b4b4;
Tffa657uint32_t Te6edf3freq Tff7b72= Te6edf3getFrequencyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3bw Tff7b72=Tff7b72= T79c0ff9 Tff7b72&Tff7b72& Tb4b4b4(T79c0ff410E6 Tff7b72<Tff7b72= Te6edf3freqTb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Te6edf3freq Tff7b72<Tff7b72= T79c0ff525E6Tb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_HIGH_BW_OPTIMIZE_1_7XTb4b4b4, T79c0ff0x02Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_HIGH_BW_OPTIMIZE_2_7XTb4b4b4, T79c0ff0x7fTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3bw Tff7b72=Tff7b72= T79c0ff9 Tff7b72&Tff7b72& Tb4b4b4(T79c0ff820E6 Tff7b72<Tff7b72= Te6edf3freqTb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Te6edf3freq Tff7b72<Tff7b72= T79c0ff1020E6Tb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_HIGH_BW_OPTIMIZE_1_7XTb4b4b4, T79c0ff0x02Tb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_HIGH_BW_OPTIMIZE_2_7XTb4b4b4, T79c0ff0x64Tb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_HIGH_BW_OPTIMIZE_1_7XTb4b4b4, T79c0ff0x03Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx127xTff7b72:Tff7b72:Te6edf3handleDio0RiseTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657int Te6edf3irqFlags Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_IRQ_FLAGS_7XTb4b4b4)Tb4b4b4;
T8b949e// Clear IRQs
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_IRQ_FLAGS_7XTb4b4b4, Te6edf3irqFlagsTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3irqFlags Tff7b72& Te6edf3IRQ_PAYLOAD_CRC_ERROR_MASK_7XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3_packetIndex Tff7b72= T79c0ff0Tb4b4b4;
Tffa657int Te6edf3packetLength Tff7b72= Te6edf3_implicitHeaderMode Tff7b72? Te6edf3readRegisterTb4b4b4(Te6edf3REG_PAYLOAD_LENGTH_7XTb4b4b4) Tff7b72: Te6edf3readRegisterTb4b4b4(Te6edf3REG_RX_NB_BYTES_7XTb4b4b4)Tb4b4b4;
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FIFO_ADDR_PTR_7XTb4b4b4, Te6edf3readRegisterTb4b4b4(Te6edf3REG_FIFO_RX_CURRENT_ADDR_7XTb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_onReceiveTb4b4b4) Tb4b4b4{ Te6edf3_onReceiveTb4b4b4(Te6edf3_indexTb4b4b4, Te6edf3packetLengthTb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_FIFO_ADDR_PTR_7XTb4b4b4, T79c0ff0Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657bool Te6edf3ISR_VECT Te6edf3sx127xTff7b72:Tff7b72:Te6edf3getPacketValidityTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657int Te6edf3irqFlags Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_IRQ_FLAGS_7XTb4b4b4)Tb4b4b4;
T8b949e// Clear IRQs
Te6edf3writeRegisterTb4b4b4(Te6edf3REG_IRQ_FLAGS_7XTb4b4b4, Te6edf3irqFlagsTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3irqFlags Tff7b72& Te6edf3IRQ_PAYLOAD_CRC_ERROR_MASK_7XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Tff7b72return Tffa657trueTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Tff7b72return Tffa657falseTb4b4b4;
Tb4b4b4}
Tb4b4b4}
T8b949e// SX128x registers
Tff7b72#Tff7b72define OP_RF_FREQ_8X 0x86
Tff7b72#Tff7b72define OP_SLEEP_8X 0x84
Tff7b72#Tff7b72define OP_STANDBY_8X 0x80
Tff7b72#Tff7b72define OP_TX_8X 0x83
Tff7b72#Tff7b72define OP_RX_8X 0x82
Tff7b72#Tff7b72define OP_SET_IRQ_FLAGS_8X 0x8D T8b949e// also provides info such as
T8b949e// preamble detection, etc for
T8b949e// knowing when it's safe to switch
T8b949e// antenna modes
Tff7b72#Tff7b72define OP_CLEAR_IRQ_STATUS_8X 0x97
Tff7b72#Tff7b72define OP_GET_IRQ_STATUS_8X 0x15
Tff7b72#Tff7b72define OP_RX_BUFFER_STATUS_8X 0x17
Tff7b72#Tff7b72define OP_PACKET_STATUS_8X 0x1D T8b949e// get snr & rssi of last packet
Tff7b72#Tff7b72define OP_CURRENT_RSSI_8X 0x1F
Tff7b72#Tff7b72define OP_MODULATION_PARAMS_8X 0x8B T8b949e// bw, sf, cr, etc.
Tff7b72#Tff7b72define OP_PACKET_PARAMS_8X 0x8C T8b949e// crc, preamble, payload length, etc.
Tff7b72#Tff7b72define OP_STATUS_8X 0xC0
Tff7b72#Tff7b72define OP_TX_PARAMS_8X 0x8E T8b949e// set dbm, etc
Tff7b72#Tff7b72define OP_PACKET_TYPE_8X 0x8A
Tff7b72#Tff7b72define OP_BUFFER_BASE_ADDR_8X 0x8F
Tff7b72#Tff7b72define OP_READ_REGISTER_8X 0x19
Tff7b72#Tff7b72define OP_WRITE_REGISTER_8X 0x18
Tff7b72#Tff7b72define IRQ_TX_DONE_MASK_8X 0x01
Tff7b72#Tff7b72define IRQ_RX_DONE_MASK_8X 0x02
Tff7b72#Tff7b72define IRQ_HEADER_DET_MASK_8X 0x10
Tff7b72#Tff7b72define IRQ_HEADER_ERROR_MASK_8X 0x20
Tff7b72#Tff7b72define IRQ_PAYLOAD_CRC_ERROR_MASK_8X 0x40
Tff7b72#Tff7b72define MODE_LONG_RANGE_MODE_8X 0x01
Tff7b72#Tff7b72define OP_FIFO_WRITE_8X 0x1A
Tff7b72#Tff7b72define OP_FIFO_READ_8X 0x1B
Tff7b72#Tff7b72define IRQ_PREAMBLE_DET_MASK_8X 0x80
Tff7b72#Tff7b72define REG_PACKET_SIZE 0x901
Tff7b72#Tff7b72define REG_FIRM_VER_MSB 0x154
Tff7b72#Tff7b72define REG_FIRM_VER_LSB 0x153
Tff7b72#Tff7b72define XTAL_FREQ_8X (double)52000000
Tff7b72#Tff7b72define FREQ_DIV_8X (double)pow(2.0, 18.0)
Tff7b72#Tff7b72define FREQ_STEP_8X (double)(XTAL_FREQ_8X Tff7b72/Tff7b72 FREQ_DIV_8X)
Te6edf3sx128xTff7b72:Tff7b72:Te6edf3sx128xTb4b4b4(Tffa657uint8_t Te6edf3indexTb4b4b4, Te6edf3SPIClassTff7b72* Te6edf3spiTb4b4b4, Tffa657bool Te6edf3tcxoTb4b4b4, Tffa657int Te6edf3ssTb4b4b4, Tffa657int Te6edf3sclkTb4b4b4, Tffa657int Te6edf3mosiTb4b4b4, Tffa657int Te6edf3misoTb4b4b4, Tffa657int Te6edf3resetTb4b4b4, Tffa657int Te6edf3dio0Tb4b4b4, Tffa657int Te6edf3busyTb4b4b4, Tffa657int Te6edf3rxenTb4b4b4, Tffa657int Te6edf3txenTb4b4b4) Tff7b72:
Te6edf3RadioInterfaceTb4b4b4(Te6edf3indexTb4b4b4)Tb4b4b4,
Te6edf3_spiSettingsTb4b4b4(T79c0ff8E6Tb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4,
Te6edf3_spiModemTb4b4b4(Te6edf3spiTb4b4b4)Tb4b4b4,
Te6edf3_ssTb4b4b4(Te6edf3ssTb4b4b4)Tb4b4b4, Te6edf3_sclkTb4b4b4(Te6edf3sclkTb4b4b4)Tb4b4b4, Te6edf3_mosiTb4b4b4(Te6edf3mosiTb4b4b4)Tb4b4b4, Te6edf3_misoTb4b4b4(Te6edf3misoTb4b4b4)Tb4b4b4, Te6edf3_resetTb4b4b4(Te6edf3resetTb4b4b4)Tb4b4b4, Te6edf3_dio0Tb4b4b4(Te6edf3dio0Tb4b4b4)Tb4b4b4,
Te6edf3_busyTb4b4b4(Te6edf3busyTb4b4b4)Tb4b4b4, Te6edf3_rxenTb4b4b4(Te6edf3rxenTb4b4b4)Tb4b4b4, Te6edf3_txenTb4b4b4(Te6edf3txenTb4b4b4)Tb4b4b4, Te6edf3_frequencyTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,
Te6edf3_bwTb4b4b4(T79c0ff0x34Tb4b4b4)Tb4b4b4, Te6edf3_crTb4b4b4(T79c0ff0x01Tb4b4b4)Tb4b4b4, Te6edf3_packetIndexTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,
Te6edf3_payloadLengthTb4b4b4(T79c0ff255Tb4b4b4)Tb4b4b4, Te6edf3_crcModeTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_fifo_tx_addr_ptrTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_fifo_rx_addr_ptrTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4,
Te6edf3_rxPacketLengthTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4, Te6edf3_preinit_doneTb4b4b4(Tffa657falseTb4b4b4)Tb4b4b4,
Te6edf3_tcxoTb4b4b4(Te6edf3tcxoTb4b4b4)Tb4b4b4, Te6edf3_preamble_eTb4b4b4(T79c0ff1Tb4b4b4)Tb4b4b4, Te6edf3_preamble_mTb4b4b4(T79c0ff1Tb4b4b4)Tb4b4b4, Te6edf3_last_preambleTb4b4b4(T79c0ff0Tb4b4b4)
Tb4b4b4{
T8b949e// overide Stream timeout value
Te6edf3setTimeoutTb4b4b4(T79c0ff0Tb4b4b4)Tb4b4b4;
T8b949e// TODO, figure out why this has to be done. Using the index to reference the
T8b949e// interface_obj list causes a crash otherwise
T8b949e//_index = getIndex();
Tb4b4b4}
Tffa657bool Te6edf3sx128xTff7b72:Tff7b72:Te6edf3preInitTb4b4b4(Tb4b4b4) Tb4b4b4{
T8b949e// setup pins
Te6edf3pinModeTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
T8b949e// set SS high
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
T8b949e// todo: check if this change causes issues on any platforms
Tff7b72#Tff7b72if MCU_VARIANT == MCU_ESP32
Tff7b72if Tb4b4b4(Te6edf3_sclk Tff7b72!Tff7b72= T79c0ff-1 Tff7b72&Tff7b72& Te6edf3_miso Tff7b72!Tff7b72= T79c0ff-1 Tff7b72&Tff7b72& Te6edf3_mosi Tff7b72!Tff7b72= T79c0ff-1 Tff7b72&Tff7b72& Te6edf3_ss Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTb4b4b4(Te6edf3_sclkTb4b4b4, Te6edf3_misoTb4b4b4, Te6edf3_mosiTb4b4b4, Te6edf3_ssTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72#Tff7b72else
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
T8b949e// check version (retry for up to 500 ms)
Tffa657long Te6edf3start Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3version_msbTb4b4b4;
Tffa657uint8_t Te6edf3version_lsbTb4b4b4;
Tff7b72while Tb4b4b4(Tb4b4b4(Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72- Te6edf3startTb4b4b4) Tff7b72< T79c0ff500Tb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72>Tff7b72= Te6edf3startTb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3version_msb Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_FIRM_VER_MSBTb4b4b4)Tb4b4b4;
Te6edf3version_lsb Tff7b72= Te6edf3readRegisterTb4b4b4(Te6edf3REG_FIRM_VER_LSBTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3version_msb Tff7b72=Tff7b72= T79c0ff0xB7 Tff7b72&Tff7b72& Te6edf3version_lsb Tff7b72=Tff7b72= T79c0ff0xA9Tb4b4b4) Tff7b72|Tff7b72| Tb4b4b4(Te6edf3version_msb Tff7b72=Tff7b72= T79c0ff0xB5 Tff7b72&Tff7b72& Te6edf3version_lsb Tff7b72=Tff7b72= T79c0ff0xA9Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72breakTb4b4b4; Tb4b4b4}
Te6edf3delayTb4b4b4(T79c0ff100Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3version_msb Tff7b72!Tff7b72= T79c0ff0xB7 Tff7b72|Tff7b72| Te6edf3version_lsb Tff7b72!Tff7b72= T79c0ff0xA9Tb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Te6edf3version_msb Tff7b72!Tff7b72= T79c0ff0xB5 Tff7b72|Tff7b72| Te6edf3version_lsb Tff7b72!Tff7b72= T79c0ff0xA9Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return Tffa657falseTb4b4b4; Tb4b4b4}
Te6edf3_preinit_done Tff7b72= Tffa657trueTb4b4b4;
Tff7b72return Tffa657trueTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3readRegisterTb4b4b4(Tffa657uint16_t Te6edf3addressTb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3singleTransferTb4b4b4(Te6edf3OP_READ_REGISTER_8XTb4b4b4, Te6edf3addressTb4b4b4, T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3writeRegisterTb4b4b4(Tffa657uint16_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4)
Tb4b4b4{
Te6edf3singleTransferTb4b4b4(Te6edf3OP_WRITE_REGISTER_8XTb4b4b4, Te6edf3addressTb4b4b4, Te6edf3valueTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3singleTransferTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint16_t Te6edf3addressTb4b4b4, Tffa657uint8_t Te6edf3valueTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3responseTb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Tb4b4b4(Te6edf3address Tff7b72& T79c0ff0xFF00Tb4b4b4) Tff7b72>Tff7b72> T79c0ff8Tb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3address Tff7b72& T79c0ff0x00FFTb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3opcode Tff7b72=Tff7b72= Te6edf3OP_READ_REGISTER_8XTb4b4b4) Tb4b4b4{ Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3response Tff7b72= Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3valueTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3responseTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_txen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3digitalWriteTb4b4b4(Te6edf3_txenTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3digitalWriteTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4; Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3txAntEnableTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_txen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3digitalWriteTb4b4b4(Te6edf3_txenTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{ Te6edf3digitalWriteTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4; Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3loraModeTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3mode Tff7b72= Te6edf3MODE_LONG_RANGE_MODE_8XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PACKET_TYPE_8XTb4b4b4, Tff7b72&Te6edf3modeTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3waitOnBusyTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657unsigned Tffa657long Te6edf3time Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72while Tb4b4b4(Te6edf3digitalReadTb4b4b4(Te6edf3_busyTb4b4b4) Tff7b72=Tff7b72= Te6edf3HIGHTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72>Tff7b72= Tb4b4b4(Te6edf3time Tff7b72+ T79c0ff100Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72breakTb4b4b4; Tb4b4b4}
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3executeOpcodeTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657uint8_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4)
Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4]Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3executeOpcodeReadTb4b4b4(Tffa657uint8_t Te6edf3opcodeTb4b4b4, Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657uint8_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3opcodeTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4)
Tb4b4b4{
Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4] Tff7b72= Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3writeBufferTb4b4b4(Tff7b72const Tffa657uint8_tTff7b72* Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3OP_FIFO_WRITE_8XTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3_fifo_tx_addr_ptrTb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4)
Tb4b4b4{
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4]Tb4b4b4)Tb4b4b4;
Te6edf3_fifo_tx_addr_ptrTff7b72+Tff7b72+Tb4b4b4;
Tb4b4b4}
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3readBufferTb4b4b4(Tffa657uint8_tTff7b72* Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Te6edf3waitOnBusyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3beginTransactionTb4b4b4(Te6edf3_spiSettingsTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3OP_FIFO_READ_8XTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(Te6edf3_fifo_rx_addr_ptrTb4b4b4)Tb4b4b4;
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< Te6edf3sizeTb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4)
Tb4b4b4{
Te6edf3bufferTb4b4b4[Te6edf3iTb4b4b4] Tff7b72= Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3transferTb4b4b4(T79c0ff0x00Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTransactionTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_ssTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setModulationParamsTb4b4b4(Tffa657uint8_t Te6edf3sfTb4b4b4, Tffa657uint8_t Te6edf3bwTb4b4b4, Tffa657uint8_t Te6edf3crTb4b4b4) Tb4b4b4{
T8b949e// because there is no access to these registers on the sx1280, we have
T8b949e// to set all these parameters at once or not at all.
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3sf Tff7b72<Tff7b72< T79c0ff4Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3bwTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Te6edf3crTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_MODULATION_PARAMS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72<Tff7b72= T79c0ff6Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(T79c0ff0x925Tb4b4b4, T79c0ff0x1ETb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72<Tff7b72= T79c0ff8Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(T79c0ff0x925Tb4b4b4, T79c0ff0x37Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72>Tff7b72= T79c0ff9Tb4b4b4) Tb4b4b4{ Te6edf3writeRegisterTb4b4b4(T79c0ff0x925Tb4b4b4, T79c0ff0x32Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3writeRegisterTb4b4b4(T79c0ff0x093CTb4b4b4, T79c0ff0x1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setPacketParamsTb4b4b4(Tffa657uint32_t Te6edf3target_preambleTb4b4b4, Tffa657uint8_t Te6edf3headermodeTb4b4b4, Tffa657uint8_t Te6edf3lengthTb4b4b4, Tffa657uint8_t Te6edf3crcTb4b4b4) Tb4b4b4{
T8b949e// because there is no access to these registers on the sx1280, we have
T8b949e// to set all these parameters at once or not at all.
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4]Tb4b4b4;
Tffa657uint32_t Te6edf3calc_preambleTb4b4b4;
T8b949e// Cap max preamble length
Tff7b72if Tb4b4b4(Te6edf3target_preamble Tff7b72>Tff7b72= T79c0ff0xF000Tb4b4b4) Te6edf3target_preamble Tff7b72= T79c0ff0xF000Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_last_preamble Tff7b72!Tff7b72= Te6edf3target_preambleTb4b4b4) Tb4b4b4{
Te6edf3_preamble_e Tff7b72= T79c0ff1Tb4b4b4;
Te6edf3_preamble_m Tff7b72= T79c0ff1Tb4b4b4;
T8b949e// calculate exponent and mantissa values for modem
Tff7b72while Tb4b4b4(Te6edf3_preamble_e Tff7b72<Tff7b72= T79c0ff15Tb4b4b4) Tb4b4b4{
Tff7b72while Tb4b4b4(Te6edf3_preamble_m Tff7b72<Tff7b72= T79c0ff15Tb4b4b4) Tb4b4b4{
Te6edf3calc_preamble Tff7b72= Te6edf3_preamble_m Tff7b72* Tb4b4b4(Te6edf3powTb4b4b4(T79c0ff2Tb4b4b4,Te6edf3_preamble_eTb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3calc_preamble Tff7b72>Tff7b72= Te6edf3target_preamble Tff7b72- T79c0ff4Tb4b4b4) Tff7b72breakTb4b4b4;
Te6edf3_preamble_mTff7b72+Tff7b72+Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3calc_preamble Tff7b72>Tff7b72= Te6edf3target_preamble Tff7b72- T79c0ff4Tb4b4b4) Tff7b72breakTb4b4b4;
Te6edf3_preamble_m Tff7b72= T79c0ff1Tb4b4b4;
Te6edf3_preamble_eTff7b72+Tff7b72+Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Tb4b4b4(Te6edf3_preamble_e Tff7b72<Tff7b72< T79c0ff4Tb4b4b4) Tff7b72| Te6edf3_preamble_mTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3headermodeTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Te6edf3lengthTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3crcTb4b4b4;
T8b949e// standard IQ setting (no inversion)
Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= T79c0ff0x40Tb4b4b4;
T8b949e// unused params
Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_PACKET_PARAMS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff7Tb4b4b4)Tb4b4b4;
Te6edf3_last_preamble Tff7b72= Te6edf3target_preambleTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3resetTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_reset Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
T8b949e// perform reset
Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3LOWTb4b4b4)Tb4b4b4;
Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;
Te6edf3digitalWriteTb4b4b4(Te6edf3_resetTb4b4b4, Te6edf3HIGHTb4b4b4)Tb4b4b4;
Te6edf3delayTb4b4b4(T79c0ff10Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657int Te6edf3sx128xTff7b72:Tff7b72:Te6edf3beginTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3resetTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_rxen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_rxenTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_txen Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_txenTb4b4b4, Te6edf3OUTPUTTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_busy Tff7b72!Tff7b72= T79c0ff-1Tb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_busyTb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3_preinit_doneTb4b4b4) Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3preInitTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{
Tff7b72return Tffa657falseTb4b4b4;
Tb4b4b4}
Tb4b4b4}
Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3loraModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3setFrequencyTb4b4b4(Te6edf3_frequencyTb4b4b4)Tb4b4b4;
T8b949e// set LNA boost
T8b949e// todo: implement this
T8b949e//writeRegister(REG_LNA, 0x96);
Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4)Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Te6edf3setTxPowerTb4b4b4(Te6edf3_txpTb4b4b4)Tb4b4b4;
T8b949e// set base addresses
Tffa657uint8_t Te6edf3basebufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_BUFFER_BASE_ADDR_8XTb4b4b4, Te6edf3basebufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3_radio_online Tff7b72= Tffa657trueTb4b4b4;
Tff7b72return T79c0ff1Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3endTb4b4b4(Tb4b4b4)
Tb4b4b4{
T8b949e// put in sleep mode
Te6edf3sleepTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// stop SPI
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3endTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3_bitrate Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3_radio_online Tff7b72= Tffa657falseTb4b4b4;
Te6edf3_preinit_done Tff7b72= Tffa657falseTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx128xTff7b72:Tff7b72:Te6edf3beginPacketTb4b4b4(Tffa657int Te6edf3implicitHeaderTb4b4b4)
Tb4b4b4{
T8b949e// put in standby mode
Te6edf3standbyTb4b4b4(Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3implicitHeaderTb4b4b4) Tb4b4b4{ Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}
Te6edf3_payloadLength Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3_fifo_tx_addr_ptr Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tff7b72return T79c0ff1Tb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx128xTff7b72:Tff7b72:Te6edf3endPacketTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Te6edf3txAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// put in single TX mode
Tffa657uint8_t Te6edf3timeoutTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_8XTb4b4b4, Te6edf3timeoutTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
T8b949e// Wait for TX done
Tffa657bool Te6edf3timed_out Tff7b72= Tffa657falseTb4b4b4;
Tffa657uint32_t Te6edf3w_timeout Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tff7b72+Tb4b4b4(Te6edf3getAirtimeTb4b4b4(Te6edf3_payloadLengthTb4b4b4)Tff7b72* Te6edf3MODEM_TIMEOUT_MULTTb4b4b4)Tb4b4b4;
Tff7b72while Tb4b4b4(Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72< Te6edf3w_timeoutTb4b4b4) Tff7b72&Tff7b72& Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_TX_DONE_MASK_8XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4)Tb4b4b4) Tb4b4b4{
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3yieldTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3millisTb4b4b4(Tb4b4b4) Tff7b72> Te6edf3w_timeoutTb4b4b4) Tb4b4b4{ Te6edf3timed_out Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
T8b949e// clear IRQ's
Tffa657uint8_t Te6edf3maskTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3maskTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3maskTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Te6edf3IRQ_TX_DONE_MASK_8XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_8XTb4b4b4, Te6edf3maskTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tff7b72return Tff7b72!Te6edf3timed_outTb4b4b4;
Tb4b4b4}
Tffa657bool Te6edf3sx128xTff7b72:Tff7b72:Te6edf3dcdTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657bool Te6edf3false_preamble_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tffa657uint32_t Te6edf3now Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;
Tffa657bool Te6edf3header_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3carrier_detected Tff7b72= Tffa657falseTb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_HEADER_DET_MASK_8XTb4b4b4) Tff7b72!Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3header_detected Tff7b72= Tffa657trueTb4b4b4; Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3header_detected Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72& Te6edf3IRQ_PREAMBLE_DET_MASK_8XTb4b4b4) Tff7b72!Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3carrier_detected Tff7b72= Tffa657trueTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_preamble_detected_at Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3_preamble_detected_at Tff7b72= Te6edf3nowTb4b4b4; Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3now Tff7b72- Te6edf3_preamble_detected_at Tff7b72> Te6edf3_lora_preamble_time_ms Tff7b72+ Te6edf3_lora_header_time_msTb4b4b4) Tb4b4b4{
Te6edf3_preamble_detected_at Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3header_detectedTb4b4b4) Tb4b4b4{ Te6edf3false_preamble_detected Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tffa657uint8_t Te6edf3clearbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; Te6edf3clearbufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3IRQ_PREAMBLE_DET_MASK_8XTb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_8XTb4b4b4, Te6edf3clearbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
T8b949e// TODO: Maybe there's a way of unlatching the RSSI
T8b949e// status without re-activating receive mode?
Tff7b72if Tb4b4b4(Te6edf3false_preamble_detectedTb4b4b4) Tb4b4b4{ Te6edf3receiveTb4b4b4(Tb4b4b4)Tb4b4b4; Tb4b4b4}
Tff7b72return Te6edf3carrier_detectedTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3currentRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_CURRENT_RSSI_8XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3byteTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3currentRssiTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_CURRENT_RSSI_8XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3rssi Tff7b72= Tff7b72-Te6edf3byte Tff7b72/ T79c0ff2Tb4b4b4;
Tff7b72return Te6edf3rssiTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3packetRssiRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff5Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3packetRssiTb4b4b4(Tffa657uint8_t Te6edf3pkt_snr_rawTb4b4b4) Tb4b4b4{
T8b949e// may need more calculations here
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff5Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3pkt_rssi Tff7b72= Tff7b72-Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72/ T79c0ff2Tb4b4b4;
Tff7b72return Te6edf3pkt_rssiTb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3packetSnrRawTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff5Tb4b4b4)Tb4b4b4;
Tff7b72return Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;
Tb4b4b4}
Tffa657float Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3packetSnrTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_PACKET_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff5Tb4b4b4)Tb4b4b4;
Tff7b72return Tffa657floatTb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4) Tff7b72* T79c0ff0.25Tb4b4b4;
Tb4b4b4}
Tffa657long Te6edf3sx128xTff7b72:Tff7b72:Te6edf3packetFrequencyErrorTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tffa657int32_t Te6edf3freqError Tff7b72= T79c0ff0Tb4b4b4;
T8b949e// todo: implement this, page 120 of sx1280 datasheet
Tff7b72const Tffa657float Te6edf3fError Tff7b72= T79c0ff0.0Tb4b4b4;
Tff7b72return Tff7b72static_castTff7b72<Tffa657longTff7b72>Tb4b4b4(Te6edf3fErrorTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657size_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tffa657uint8_t Te6edf3byteTb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3writeTb4b4b4(Tff7b72&Te6edf3byteTb4b4b4, Tff7b72sizeofTb4b4b4(Te6edf3byteTb4b4b4)Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657size_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3writeTb4b4b4(Tff7b72const Tffa657uint8_t Tff7b72*Te6edf3bufferTb4b4b4, Tffa657size_t Te6edf3sizeTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3_payloadLength Tff7b72+ Te6edf3sizeTb4b4b4) Tff7b72> Te6edf3MAX_PKT_LENGTHTb4b4b4) Tb4b4b4{
Te6edf3size Tff7b72= Te6edf3MAX_PKT_LENGTH Tff7b72- Te6edf3_payloadLengthTb4b4b4;
Tb4b4b4}
T8b949e// write data
Te6edf3writeBufferTb4b4b4(Te6edf3bufferTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;
Te6edf3_payloadLength Tff7b72= Te6edf3_payloadLength Tff7b72+ Te6edf3sizeTb4b4b4;
Tff7b72return Te6edf3sizeTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3availableTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3_rxPacketLength Tff7b72- Te6edf3_packetIndexTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3readTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{
Tff7b72return T79c0ff-1Tb4b4b4;
Tb4b4b4}
T8b949e// if received new packet
Tff7b72if Tb4b4b4(Te6edf3_packetIndex Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_8XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tffa657int Te6edf3sizeTb4b4b4;
T8b949e// If implicit header mode is enabled, read packet length as payload length instead.
T8b949e// See SX1280 datasheet v3.2, page 92
Tff7b72if Tb4b4b4(Te6edf3_implicitHeaderMode Tff7b72=Tff7b72= T79c0ff0x80Tb4b4b4) Tb4b4b4{
Te6edf3size Tff7b72= Te6edf3_payloadLengthTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3size Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;
Tb4b4b4}
Te6edf3_fifo_rx_addr_ptr Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff1Tb4b4b4]Tb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3size Tff7b72> T79c0ff255Tb4b4b4) Tb4b4b4{ Te6edf3size Tff7b72= T79c0ff255Tb4b4b4; Tb4b4b4}
Te6edf3readBufferTb4b4b4(Te6edf3_packetTb4b4b4, Te6edf3sizeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3byte Tff7b72= Te6edf3_packetTb4b4b4[Te6edf3_packetIndexTb4b4b4]Tb4b4b4;
Te6edf3_packetIndexTff7b72+Tff7b72+Tb4b4b4;
Tff7b72return Te6edf3byteTb4b4b4;
Tb4b4b4}
Tffa657int Te6edf3sx128xTff7b72:Tff7b72:Te6edf3peekTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Tff7b72!Te6edf3availableTb4b4b4(Tb4b4b4)Tb4b4b4) Tb4b4b4{ Tff7b72return T79c0ff-1Tb4b4b4; Tb4b4b4}
Tffa657uint8_t Te6edf3b Tff7b72= Te6edf3_packetTb4b4b4[Te6edf3_packetIndexTb4b4b4]Tb4b4b4;
Tff7b72return Te6edf3bTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3flushTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3onReceiveTb4b4b4(Tffa657voidTb4b4b4(Tff7b72*Te6edf3callbackTb4b4b4)Tb4b4b4(Tffa657uint8_tTb4b4b4, Tffa657intTb4b4b4)Tb4b4b4)
Tb4b4b4{
Te6edf3_onReceive Tff7b72= Te6edf3callbackTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3callbackTb4b4b4) Tb4b4b4{
Te6edf3pinModeTb4b4b4(Te6edf3_dio0Tb4b4b4, Te6edf3INPUTTb4b4b4)Tb4b4b4;
T8b949e// set preamble and header detection irqs, plus dio0 mask
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff8Tb4b4b4]Tb4b4b4;
T8b949e// set irq masks, enable all
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0xFFTb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xFFTb4b4b4;
T8b949e// On the SX1280, no RxDone IRQ is generated if a packet is received with
T8b949e// an invalid header, but the modem will be taken out of single RX mode.
T8b949e// This can cause the modem to not receive packets until it is reset
T8b949e// again. This is documented as Errata 16.2 in the SX1280 datasheet v3.2
T8b949e// (page 150) Below, the header error IRQ is mapped to dio0 so that the
T8b949e// modem can be set into RX mode again on reception of a corrupted
T8b949e// header.
T8b949e// set dio0 masks
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Te6edf3IRQ_RX_DONE_MASK_8X Tff7b72| Te6edf3IRQ_HEADER_ERROR_MASK_8XTb4b4b4;
T8b949e// set dio1 masks
Te6edf3bufTb4b4b4[T79c0ff4Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff5Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
T8b949e// set dio2 masks
Te6edf3bufTb4b4b4[T79c0ff6Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff7Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_SET_IRQ_FLAGS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff8Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3usingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
T8b949e// make function available
Tff7b72extern Tffa657void Tb4b4b4(Tff7b72*Te6edf3onIntRiseTb4b4b4[Te6edf3INTERFACE_COUNTTb4b4b4]Tb4b4b4)Tb4b4b4(Tffa657voidTb4b4b4)Tb4b4b4;
Te6edf3attachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4, Te6edf3onIntRiseTb4b4b4[Te6edf3_indexTb4b4b4]Tb4b4b4, Te6edf3RISINGTb4b4b4)Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3detachInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72ifdef SPI_HAS_NOTUSINGINTERRUPT
Te6edf3_spiModemTff7b72-Tff7b72>Te6edf3notUsingInterruptTb4b4b4(Te6edf3digitalPinToInterruptTb4b4b4(Te6edf3_dio0Tb4b4b4)Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3receiveTb4b4b4(Tffa657int Te6edf3sizeTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3size Tff7b72> T79c0ff0Tb4b4b4) Tb4b4b4{
Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// tell radio payload length
T8b949e//_rxPacketLength = size;
T8b949e//_payloadLength = size;
T8b949e//setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Te6edf3rxAntEnableTb4b4b4(Tb4b4b4)Tb4b4b4;
T8b949e// On the SX1280, there is a bug which can cause the busy line
T8b949e// to remain high if a high amount of packets are received when
T8b949e// in continuous RX mode. This is documented as Errata 16.1 in
T8b949e// the SX1280 datasheet v3.2 (page 149)
T8b949e// Therefore, the modem is set to single RX mode below instead.
Tffa657uint8_t Te6edf3modeTb4b4b4[T79c0ff3Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4; T8b949e// single RX mode
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_RX_8XTb4b4b4, Te6edf3modeTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3standbyTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tffa657uint8_t Te6edf3byteTb4b4b4;
Tff7b72if Tb4b4b4(Te6edf3_tcxoTb4b4b4) Tb4b4b4{
T8b949e// STDBY_XOSC
Te6edf3byte Tff7b72= T79c0ff0x01Tb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
T8b949e// STDBY_RC
Te6edf3byte Tff7b72= T79c0ff0x00Tb4b4b4;
Tb4b4b4}
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_STANDBY_8XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3sleepTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tffa657uint8_t Te6edf3byte Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_SLEEP_8XTb4b4b4, Tff7b72&Te6edf3byteTb4b4b4, T79c0ff1Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3enableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{
T8b949e// todo: need to check how to implement on sx1280
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3disableTCXOTb4b4b4(Tb4b4b4) Tb4b4b4{
T8b949e// todo: need to check how to implement on sx1280
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setTxPowerTb4b4b4(Tffa657int Te6edf3levelTb4b4b4, Tffa657int Te6edf3outputPinTb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3tx_bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Tff7b72#Tff7b72if BOARD_VARIANT == MODEL_13 || BOARD_VARIANT == MODEL_14 || BOARD_VARIANT == MODEL_21
T8b949e// RAK4631 with WisBlock SX1280 module (LIBSYS002 rev 1.3)
T8b949e// Power range on this model is roughly -6 dBm to 20 dBm
Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff20Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff20Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff-6Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff-6Tb4b4b4; Tb4b4b4}
Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;
Tffa657int Te6edf3reg_valueTb4b4b4;
Tff7b72switch Tb4b4b4(Te6edf3levelTb4b4b4) Tb4b4b4{
Tff7b72case T79c0ff-6Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-18Tb4b4b4; T8b949e// -6.3 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff-5Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-17Tb4b4b4; T8b949e// -5.4 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff-4Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-16Tb4b4b4; T8b949e// -3.9 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff-3Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-15Tb4b4b4; T8b949e// -2.9 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff-2Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-14Tb4b4b4; T8b949e// -2 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff-1Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-13Tb4b4b4; T8b949e// CANNOT SET, BUG??
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff0Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-12Tb4b4b4; T8b949e// -0.4 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff1Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-10Tb4b4b4; T8b949e// 1.1 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff2Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-9Tb4b4b4; T8b949e// 2.4 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff3Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-8Tb4b4b4; T8b949e// 3 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff4Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-7Tb4b4b4; T8b949e// 4.1 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff5Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-6Tb4b4b4; T8b949e// 5.1 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff6Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-5Tb4b4b4; T8b949e// 6 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff7Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-4Tb4b4b4; T8b949e// 7.3 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff8Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-3Tb4b4b4; T8b949e// 8.3 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff9Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-2Tb4b4b4; T8b949e// 9.2 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff10Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-1Tb4b4b4; T8b949e// 10.3 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff11Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff0Tb4b4b4; T8b949e// 11.4 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff12Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff1Tb4b4b4; T8b949e// 12.4 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff13Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff2Tb4b4b4; T8b949e// 13.5 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff14Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff2Tb4b4b4; T8b949e// 13.5 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff15Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff3Tb4b4b4; T8b949e// 14.3 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff16Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff5Tb4b4b4; T8b949e// 16.4 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff17Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff6Tb4b4b4; T8b949e// 17.1 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff18Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff8Tb4b4b4; T8b949e// 18.5 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff19Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff10Tb4b4b4; T8b949e// 19.2 dBm
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff20Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff13Tb4b4b4; T8b949e// 20.1 dBm
Tff7b72breakTb4b4b4;
Tff7b72defaultTff7b72:
Te6edf3reg_value Tff7b72= T79c0ff-18Tb4b4b4;
Tff7b72breakTb4b4b4;
Tb4b4b4}
Te6edf3tx_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3reg_value Tff7b72+ T79c0ff18Tb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xE0Tb4b4b4; T8b949e// ramping time - 20 microseconds
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_PARAMS_8XTb4b4b4, Te6edf3tx_bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72elif BOARD_VARIANT == MODEL_AC
T8b949e// T3S3 SX1280 PA
Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff20Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff20Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff0Tb4b4b4) Tb4b4b4{ Te6edf3level Tff7b72= T79c0ff0Tb4b4b4; Tb4b4b4}
Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;
Tffa657int Te6edf3reg_valueTb4b4b4;
Tff7b72switch Tb4b4b4(Te6edf3levelTb4b4b4) Tb4b4b4{
Tff7b72case T79c0ff0Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-18Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff1Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-17Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff2Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-16Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff3Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-15Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff4Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-14Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff5Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-13Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff6Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-12Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff7Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-10Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff8Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-9Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff9Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-8Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff10Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-7Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff11Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-6Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff12Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-5Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff13Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-4Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff14Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-3Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff15Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-2Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff16Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff-1Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff17Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff18Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff1Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff19Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff2Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72case T79c0ff20Tb4b4b4:
Te6edf3reg_value Tff7b72= T79c0ff3Tb4b4b4;
Tff7b72breakTb4b4b4;
Tff7b72defaultTff7b72:
Te6edf3reg_value Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72breakTb4b4b4;
Tb4b4b4}
Te6edf3tx_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3reg_valueTb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xE0Tb4b4b4; T8b949e// ramping time - 20 microseconds
Tff7b72#Tff7b72else
T8b949e// For SX1280 boards with no specific PA requirements
Tff7b72if Tb4b4b4(Te6edf3level Tff7b72> T79c0ff13Tb4b4b4) Tb4b4b4{
Te6edf3level Tff7b72= T79c0ff13Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3level Tff7b72< T79c0ff-18Tb4b4b4) Tb4b4b4{
Te6edf3level Tff7b72= T79c0ff-18Tb4b4b4;
Tb4b4b4}
Te6edf3_txp Tff7b72= Te6edf3levelTb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Te6edf3level Tff7b72+ T79c0ff18Tb4b4b4;
Te6edf3tx_bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0xE0Tb4b4b4; T8b949e// ramping time - 20 microseconds
Tff7b72#Tff7b72endif
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_TX_PARAMS_8XTb4b4b4, Te6edf3tx_bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657int8_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3getTxPowerTb4b4b4(Tb4b4b4) Tb4b4b4{
Tff7b72return Te6edf3_txpTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setFrequencyTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4) Tb4b4b4{
Te6edf3_frequency Tff7b72= Te6edf3frequencyTb4b4b4;
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff3Tb4b4b4]Tb4b4b4;
Tffa657uint32_t Te6edf3freq Tff7b72= Tb4b4b4(Tffa657uint32_tTb4b4b4)Tb4b4b4(Tb4b4b4(Tffa657doubleTb4b4b4)Te6edf3frequency Tff7b72/ Tb4b4b4(Tffa657doubleTb4b4b4)Te6edf3FREQ_STEP_8XTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff16Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= Tb4b4b4(Tb4b4b4(Te6edf3freq Tff7b72>Tff7b72> T79c0ff8Tb4b4b4) Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4(Te6edf3freq Tff7b72& T79c0ff0xFFTb4b4b4)Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_RF_FREQ_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff3Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint32_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3getFrequencyTb4b4b4(Tb4b4b4) Tb4b4b4{
T8b949e// we can't read the frequency on the sx1280
Tffa657uint32_t Te6edf3frequency Tff7b72= Te6edf3_frequencyTb4b4b4;
Tff7b72return Te6edf3frequencyTb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setSpreadingFactorTb4b4b4(Tffa657int Te6edf3sfTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72< T79c0ff5Tb4b4b4) Tb4b4b4{
Te6edf3sf Tff7b72= T79c0ff5Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sf Tff7b72> T79c0ff12Tb4b4b4) Tb4b4b4{
Te6edf3sf Tff7b72= T79c0ff12Tb4b4b4;
Tb4b4b4}
Te6edf3_sf Tff7b72= Te6edf3sfTb4b4b4;
Te6edf3setModulationParamsTb4b4b4(Te6edf3sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4)Tb4b4b4;
Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3getSpreadingFactorTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3_sfTb4b4b4;
Tb4b4b4}
Tffa657uint32_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3getSignalBandwidthTb4b4b4(Tb4b4b4)
Tb4b4b4{
Tffa657int Te6edf3bw Tff7b72= Te6edf3_bwTb4b4b4;
Tff7b72switch Tb4b4b4(Te6edf3bwTb4b4b4) Tb4b4b4{
Tff7b72case T79c0ff0x34Tb4b4b4: Tff7b72return T79c0ff203.125E3Tb4b4b4;
Tff7b72case T79c0ff0x26Tb4b4b4: Tff7b72return T79c0ff406.25E3Tb4b4b4;
Tff7b72case T79c0ff0x18Tb4b4b4: Tff7b72return T79c0ff812.5E3Tb4b4b4;
Tff7b72case T79c0ff0x0ATb4b4b4: Tff7b72return T79c0ff1625E3Tb4b4b4;
Tb4b4b4}
Tff7b72return T79c0ff0Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3_sf Tff7b72> T79c0ff10Tb4b4b4) Tb4b4b4{ Te6edf3_ldro Tff7b72= Tffa657trueTb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3_ldro Tff7b72= Tffa657falseTb4b4b4; Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3optimizeModemSensitivityTb4b4b4(Tb4b4b4)Tb4b4b4{
T8b949e// todo: check if there's anything the sx1280 can do here
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setSignalBandwidthTb4b4b4(Tffa657uint32_t Te6edf3sbwTb4b4b4)
Tb4b4b4{
Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff203.125E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x34Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff406.25E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x26Tb4b4b4; Tb4b4b4}
Tff7b72else Tff7b72if Tb4b4b4(Te6edf3sbw Tff7b72<Tff7b72= T79c0ff812.5E3Tb4b4b4) Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x18Tb4b4b4; Tb4b4b4}
Tff7b72else Tb4b4b4{ Te6edf3_bw Tff7b72= T79c0ff0x0ATb4b4b4; Tb4b4b4}
Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4)Tb4b4b4;
Te6edf3handleLowDataRateTb4b4b4(Tb4b4b4)Tb4b4b4;
Te6edf3optimizeModemSensitivityTb4b4b4(Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setCodingRate4Tb4b4b4(Tffa657int Te6edf3denominatorTb4b4b4) Tb4b4b4{
T8b949e// TODO: add support for new interleaving scheme, see page 117 of sx1280 datasheet
Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72< T79c0ff5Tb4b4b4) Tb4b4b4{
Te6edf3denominator Tff7b72= T79c0ff5Tb4b4b4;
Tb4b4b4} Tff7b72else Tff7b72if Tb4b4b4(Te6edf3denominator Tff7b72> T79c0ff8Tb4b4b4) Tb4b4b4{
Te6edf3denominator Tff7b72= T79c0ff8Tb4b4b4;
Tb4b4b4}
Te6edf3_cr Tff7b72= Te6edf3denominator Tff7b72- T79c0ff4Tb4b4b4;
T8b949e// todo: add support for new interleaving scheme, see page 117 of sx1280
T8b949e// datasheet
T8b949e// update cr values for sx1280's use
Te6edf3setModulationParamsTb4b4b4(Te6edf3_sfTb4b4b4, Te6edf3_bwTb4b4b4, Te6edf3_crTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3getCodingRate4Tb4b4b4(Tb4b4b4)
Tb4b4b4{
Tff7b72return Te6edf3_cr Tff7b72+ T79c0ff4Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setPreambleLengthTb4b4b4(Tffa657long Te6edf3lengthTb4b4b4)
Tb4b4b4{
Te6edf3_preambleLength Tff7b72= Te6edf3lengthTb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3lengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setSyncWordTb4b4b4(Tffa657int Te6edf3swTb4b4b4)
Tb4b4b4{
T8b949e// not implemented
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3enableCrcTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3_crcMode Tff7b72= T79c0ff0x20Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3disableCrcTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3_crcMode Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657uint8_t Te6edf3sx128xTff7b72:Tff7b72:Te6edf3randomTb4b4b4(Tb4b4b4)
Tb4b4b4{
T8b949e// todo: implement
Tff7b72return T79c0ff0x4Tb4b4b4; T8b949e//chosen by fair die roll
T8b949e//guarenteed to be random
T8b949e//https://xkcd.com/221/
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3setSPIFrequencyTb4b4b4(Tffa657uint32_t Te6edf3frequencyTb4b4b4)
Tb4b4b4{
Te6edf3_spiSettings Tff7b72= Te6edf3SPISettingsTb4b4b4(Te6edf3frequencyTb4b4b4, Te6edf3MSBFIRSTTb4b4b4, Te6edf3SPI_MODE0Tb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3dumpRegistersTb4b4b4(Te6edf3StreamTff7b72& Te6edf3outTb4b4b4)
Tb4b4b4{
Tff7b72for Tb4b4b4(Tffa657int Te6edf3i Tff7b72= T79c0ff0Tb4b4b4; Te6edf3i Tff7b72< T79c0ff128Tb4b4b4; Te6edf3iTff7b72+Tff7b72+Tb4b4b4) Tb4b4b4{
Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Ta5d6ff"Ta5d6ff0xTa5d6ff"Tb4b4b4)Tb4b4b4;
Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Te6edf3iTb4b4b4, Te6edf3HEXTb4b4b4)Tb4b4b4;
Te6edf3outTb4b4b4.Te6edf3printTb4b4b4(Ta5d6ff"Ta5d6ff: 0xTa5d6ff"Tb4b4b4)Tb4b4b4;
Te6edf3outTb4b4b4.Te6edf3printlnTb4b4b4(Te6edf3readRegisterTb4b4b4(Te6edf3iTb4b4b4)Tb4b4b4, Te6edf3HEXTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3explicitHeaderModeTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3_implicitHeaderMode Tff7b72= T79c0ff0Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3implicitHeaderModeTb4b4b4(Tb4b4b4)
Tb4b4b4{
Te6edf3_implicitHeaderMode Tff7b72= T79c0ff0x80Tb4b4b4;
Te6edf3setPacketParamsTb4b4b4(Te6edf3_preambleLengthTb4b4b4, Te6edf3_implicitHeaderModeTb4b4b4, Te6edf3_payloadLengthTb4b4b4, Te6edf3_crcModeTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tffa657void Te6edf3sx128xTff7b72:Tff7b72:Te6edf3handleDio0RiseTb4b4b4(Tb4b4b4)
Tb4b4b4{
T8b949e// received a packet
Te6edf3_packetIndex Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint8_t Te6edf3rxbufTb4b4b4[T79c0ff2Tb4b4b4] Tff7b72= Tb4b4b4{T79c0ff0Tb4b4b4}Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_RX_BUFFER_STATUS_8XTb4b4b4, Te6edf3rxbufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
T8b949e// If implicit header mode is enabled, read packet length as payload length instead.
T8b949e// See SX1280 datasheet v3.2, page 92
Tff7b72if Tb4b4b4(Te6edf3_implicitHeaderMode Tff7b72=Tff7b72= T79c0ff0x80Tb4b4b4) Tb4b4b4{
Te6edf3_rxPacketLength Tff7b72= Te6edf3_payloadLengthTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Te6edf3_rxPacketLength Tff7b72= Te6edf3rxbufTb4b4b4[T79c0ff0Tb4b4b4]Tb4b4b4;
Tb4b4b4}
Tff7b72if Tb4b4b4(Te6edf3_onReceiveTb4b4b4) Tb4b4b4{
Te6edf3_onReceiveTb4b4b4(Te6edf3_indexTb4b4b4, Te6edf3_rxPacketLengthTb4b4b4)Tb4b4b4;
Tb4b4b4}
Tb4b4b4}
Tffa657bool Te6edf3ISR_VECT Te6edf3sx128xTff7b72:Tff7b72:Te6edf3getPacketValidityTb4b4b4(Tb4b4b4) Tb4b4b4{
Tffa657uint8_t Te6edf3bufTb4b4b4[T79c0ff2Tb4b4b4]Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff0Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72= T79c0ff0x00Tb4b4b4;
Te6edf3executeOpcodeReadTb4b4b4(Te6edf3OP_GET_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Te6edf3executeOpcodeTb4b4b4(Te6edf3OP_CLEAR_IRQ_STATUS_8XTb4b4b4, Te6edf3bufTb4b4b4, T79c0ff2Tb4b4b4)Tb4b4b4;
Tff7b72if Tb4b4b4(Tb4b4b4(Te6edf3bufTb4b4b4[T79c0ff1Tb4b4b4] Tff7b72& Te6edf3IRQ_PAYLOAD_CRC_ERROR_MASK_8XTb4b4b4) Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Tb4b4b4{
Tff7b72return Tffa657trueTb4b4b4;
Tb4b4b4} Tff7b72else Tb4b4b4{
Tff7b72return Tffa657falseTb4b4b4;
Tb4b4b4}
Tb4b4b4}
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